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From: Jim Quinlan <james.quinlan@broadcom.com>
To: james.quinlan@broadcom.com
Cc: Jim Quinlan <james.quinlan@broadcom.com>,
	Nicolas Saenz Julienne <nsaenzjulienne@suse.de>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Rob Herring <robh@kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Florian Fainelli <f.fainelli@gmail.com>,
	bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM
	BCM7XXX ARM ARCHITECTURE),
	Andrew Murray <amurray@thegoodpenguin.co.uk>,
	Jeremy Linton <jeremy.linton@arm.com>,
	linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM
	BCM2711/BCM2835 ARM ARCHITECTURE),
	linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM
	BCM2711/BCM2835 ARM ARCHITECTURE),
	linux-pci@vger.kernel.org (open list:PCI NATIVE HOST BRIDGE AND
	ENDPOINT DRIVERS), linux-kernel@vger.kernel.org (open list)
Subject: [PATCH v3 2/4] PCI: brcmstb: Fix window register offset from 4 to 8
Date: Thu,  7 May 2020 16:15:41 -0400	[thread overview]
Message-ID: <20200507201544.43432-3-james.quinlan@broadcom.com> (raw)
In-Reply-To: <20200507201544.43432-1-james.quinlan@broadcom.com>

From: Jim Quinlan <jquinlan@broadcom.com>

The outbound memory window registers were being referenced
with an incorrect stride offset.  This probably wasn't noticed
previously as there was likely only one such window employed.

Signed-off-by: Jim Quinlan <jquinlan@broadcom.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>

Fixes: c0452137034b ("PCI: brcmstb: Add Broadcom STB PCIe host controller driver")
---
 drivers/pci/controller/pcie-brcmstb.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 454917ee9241..5b0dec5971b8 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -54,11 +54,11 @@
 
 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO		0x400c
 #define PCIE_MEM_WIN0_LO(win)	\
-		PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4)
+		PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 8)
 
 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI		0x4010
 #define PCIE_MEM_WIN0_HI(win)	\
-		PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4)
+		PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 8)
 
 #define PCIE_MISC_RC_BAR1_CONFIG_LO			0x402c
 #define  PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK		0x1f
-- 
2.17.1


  parent reply	other threads:[~2020-05-07 20:16 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-07 20:15 [PATCH v3 0/4] PCI: brcmstb: Some minor fixes/features Jim Quinlan
2020-05-07 20:15 ` [PATCH v3 1/4] PCI: brcmstb: Don't clk_put() a managed clock Jim Quinlan
2020-05-07 20:17   ` Florian Fainelli
2020-05-07 20:15 ` Jim Quinlan [this message]
2020-05-07 20:15 ` [PATCH v3 3/4] dt-bindings: PCI: brcmstb: New prop 'aspm-no-l0s' Jim Quinlan
2020-05-08  1:11   ` Rob Herring
2020-05-07 20:15 ` [PATCH v3 4/4] PCI: brcmstb: Disable L0s component of ASPM if requested Jim Quinlan
2020-05-11 10:52 ` [PATCH v3 0/4] PCI: brcmstb: Some minor fixes/features Lorenzo Pieralisi

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