Re: [PATCH v3 54/75] x86/sev-es: Handle DR7 read/write events

Borislav Petkov
2020-05-25T10:59:45Z

On Tue, Apr 28, 2020 at 05:17:04PM +0200, Joerg Roedel wrote:
> +static enum es_result vc_handle_dr7_write(struct ghcb *ghcb,
> + struct es_em_ctxt *ctxt)
> +{
> + struct sev_es_runtime_data *data = this_cpu_read(runtime_data);
> + long val, *reg = vc_insn_get_rm(ctxt);
> + enum es_result ret;
> +
> + if (!reg)
> + return ES_DECODE_FAILED;
> +
> + val = *reg;
> +
> + /* Upper 32 bits must be written as zeroes */
> + if (val >> 32) {
> + ctxt->fi.vector = X86_TRAP_GP;
> + ctxt->fi.error_code = 0;
> + return ES_EXCEPTION;
> + }
> +
> + /* Clear out other reservered bits and set bit 10 */

"reserved"

> + val = (val & 0xffff23ffL) | BIT(10);
> +
> + /* Early non-zero writes to DR7 are not supported */
> + if (!data && (val & ~DR7_RESET_VALUE))
> + return ES_UNSUPPORTED;
> +
> + /* Using a value of 0 for ExitInfo1 means RAX holds the value */
> + ghcb_set_rax(ghcb, val);
> + ret = sev_es_ghcb_hv_call(ghcb, ctxt, SVM_EXIT_WRITE_DR7, 0, 0);
> + if (ret != ES_OK)
> + return ret;
> +
> + if (data)
> + data->dr7 = val;

Are we still returning ES_OK if !data?

> +
> + return ES_OK;
> +}

--
Regards/Gruss,
Boris.