From: Peter Zijlstra <peterz@infradead.org>
To: Andy Lutomirski <luto@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>,
LKML <linux-kernel@vger.kernel.org>, X86 ML <x86@kernel.org>
Subject: Re: [RFC][PATCH 0/4] x86/entry: disallow #DB more
Date: Sat, 23 May 2020 23:32:35 +0200 [thread overview]
Message-ID: <20200523213235.GB4496@worktop.programming.kicks-ass.net> (raw)
In-Reply-To: <20200523125940.GA2483@worktop.programming.kicks-ass.net>
On Sat, May 23, 2020 at 02:59:40PM +0200, Peter Zijlstra wrote:
> On Fri, May 22, 2020 at 03:13:57PM -0700, Andy Lutomirski wrote:
> > This is great, except that the unconditional DR7 write is going to
> > seriously hurt perf performance. Fortunately, no one cares about
> > perf, right? :)
>
> Good point, so the trivial optimization is below. I couldn't find
> instruction latency numbers for DRn load/stores anywhere. I'm hoping
> loads are cheap.
+ u64 empty = 0, read = 0, write = 0;
+ unsigned long dr7;
+
+ for (i=0; i<100; i++) {
+ u64 s;
+
+ s = rdtsc();
+ barrier_nospec();
+ barrier_nospec();
+ empty += rdtsc() - s;
+
+ s = rdtsc();
+ barrier_nospec();
+ dr7 = native_get_debugreg(7);
+ barrier_nospec();
+ read += rdtsc() - s;
+
+ s = rdtsc();
+ barrier_nospec();
+ native_set_debugreg(7, 0);
+ barrier_nospec();
+ write += rdtsc() - s;
+ }
+
+ printk("XXX: %ld %ld %ld\n", empty, read, write);
[ 1.628125] XXX: 2800 2404 19600
IOW, reading DR7 is basically free, and certainly cheaper than looking
at cpu_dr7 which would probably be an insta cache miss.
Which seems to suggest KVM can go pound sand. Maybe they can fix
themselves with some paravirt love.
next prev parent reply other threads:[~2020-05-23 21:32 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-22 20:47 [RFC][PATCH 0/4] x86/entry: disallow #DB more Peter Zijlstra
2020-05-22 20:47 ` [RFC][PATCH 1/4] x86/entry: Introduce local_db_{rave,restore}() Peter Zijlstra
2020-05-22 20:47 ` [RFC][PATCH 2/4] x86/entry, nmi: Disable #DB Peter Zijlstra
2020-05-22 20:47 ` [RFC][PATCH 3/4] x86/entry: Remove debug IST frobbing Peter Zijlstra
2020-05-22 20:47 ` [RFC][PATCH 4/4] x86/entry, mce: Disallow #DB during #MC Peter Zijlstra
2020-05-22 22:13 ` [RFC][PATCH 0/4] x86/entry: disallow #DB more Andy Lutomirski
2020-05-22 22:20 ` Sean Christopherson
2020-05-22 22:43 ` Andy Lutomirski
2020-05-23 12:59 ` Peter Zijlstra
2020-05-23 21:32 ` Peter Zijlstra [this message]
2020-05-25 10:02 ` Rasmus Villemoes
2020-05-25 10:40 ` Peter Zijlstra
2020-05-25 11:01 ` Peter Zijlstra
2020-05-25 17:19 ` Andy Lutomirski
2020-05-25 18:08 ` Peter Zijlstra
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