From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59F5DC433DF for ; Sat, 13 Jun 2020 20:20:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1F8EB20789 for ; Sat, 13 Jun 2020 20:20:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="TVtRDFFM" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726663AbgFMURK (ORCPT ); Sat, 13 Jun 2020 16:17:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46370 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726462AbgFMURI (ORCPT ); Sat, 13 Jun 2020 16:17:08 -0400 Received: from mail-qt1-x841.google.com (mail-qt1-x841.google.com [IPv6:2607:f8b0:4864:20::841]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9FB7DC03E96F for ; Sat, 13 Jun 2020 13:17:08 -0700 (PDT) Received: by mail-qt1-x841.google.com with SMTP id z1so9786624qtn.2 for ; Sat, 13 Jun 2020 13:17:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=XvmodwFRSbxZ4SI7zIxONP0m2KmZ4cn7dUMYubaK5Ks=; b=TVtRDFFMNSw/l66ad19EjvoamliFx2a/IbcJQJllefvOFy6pOlBriThoJJMflyHn9r mMfY2TQunbbGvbg5mEvBJGkEX/qtcUqXJjkDx++ZxZgiOhZz5j1wJHoHBQ1LIaINBS16 0WL4P9pN8Z1PexylK67mot7qXfFlTiHieZ96xUVBFxBWmlpHob9UgvAnei0Ar5u4sMtL ME2bQgH5o/RbrXViwgvrOhH4loFcfg2NEqYPo0DYsFu38uEBKBr//Jzu2EY/uMFAXTpA QYN2iOcVgDRuCs47X+Id4L8AAb3/F9DyZ7m7GaNO45gPGeCaXgtkosoQnMclldGinoZk GDgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=XvmodwFRSbxZ4SI7zIxONP0m2KmZ4cn7dUMYubaK5Ks=; b=bGXgRK+IL+fFPS152uvTO5cfDAHUUteyB+kizNOAQA3aE7MPK7FJMgTNJ4pqcONx71 idEYJqLD0QB7qAhN9m54IesPNPbC6BjAOKgxZjtaaOD2rGjYN2WofeKXbGPnVJme63Yf MXAmXuNE7otO0dDWRGh6KNR5jDnspBYP5GWauXWOJvVqlm9IPadoM2IgFSHy8EMMrKKa yvnL64vPAez5PQXmIJ+jaV1xFoi7PMp5RL11x/dXB3EZI0UxRTwMnI9M3iHxprvtlkeP /DMIYhQhsxfXl8wQO1s0ki6VmyXi526K5IFRuf9GxIsYrhdTBUYfKGxDxdAhTZbcF6yj 2Fog== X-Gm-Message-State: AOAM531h1aRkEL3RWf4MQXJFJx1Vt7ZXyJV/62dY1n5fxQ6yAyPR+Riy gjAxo5WZWp1KOE4IDvx7EHc= X-Google-Smtp-Source: ABdhPJwSVNAUudjU7V0EJt0q1PtzNAfLsF+rab1TmlO6E01e8qp0NXHIRvbCZ/1ah1drJ+1VTtPW4Q== X-Received: by 2002:ac8:4790:: with SMTP id k16mr9181655qtq.362.1592079427023; Sat, 13 Jun 2020 13:17:07 -0700 (PDT) Received: from localhost.localdomain ([72.53.229.195]) by smtp.gmail.com with ESMTPSA id n25sm6969264qkk.76.2020.06.13.13.17.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Jun 2020 13:17:06 -0700 (PDT) From: Sven Van Asbroeck X-Google-Original-From: Sven Van Asbroeck To: Shawn Guo Cc: Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1] ARM: imx6plus: enable internal routing of clk_enet_ref where possible Date: Sat, 13 Jun 2020 16:17:03 -0400 Message-Id: <20200613201703.16788-1-TheSven73@gmail.com> X-Mailer: git-send-email 2.17.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On imx6, the ethernet reference clock (clk_enet_ref) can be generated by either the imx6, or an external source (e.g. an oscillator or the PHY). When generated by the imx6, the clock source (from ANATOP) must be routed to the input of clk_enet_ref via two pads on the SoC, typically via a dedicated track on the PCB. On an imx6 plus however, there is a new setting which enables this clock to be routed internally on the SoC, from its ANATOP clock source, straight to clk_enet_ref, without having to go through the SoC pads. Board designs where the clock is generated by the imx6 should not be affected by routing the clock internally. Therefore on a plus, we can enable internal routing by default. To: Shawn Guo Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Sven Van Asbroeck --- arch/arm/mach-imx/mach-imx6q.c | 18 ++++++++++++++++++ include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 1 + 2 files changed, 19 insertions(+) Tree: next-20200613 diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 85c084a716ab..4d22567bb650 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -203,6 +203,24 @@ static void __init imx6q_1588_init(void) else pr_err("failed to find fsl,imx6q-iomuxc-gpr regmap\n"); + /* + * On imx6 plus, enet_ref from ANATOP/CCM can be internally routed to + * be the PTP clock source, instead of having to be routed through + * pads. + * Board designs which route the ANATOP/CCM clock through pads are + * unaffected when routing happens internally. So on these designs, + * route internally by default. + */ + if (clksel == IMX6Q_GPR1_ENET_CLK_SEL_ANATOP && cpu_is_imx6q() && + imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) { + if (!IS_ERR(gpr)) + regmap_update_bits(gpr, IOMUXC_GPR5, + IMX6Q_GPR5_ENET_TXCLK_SEL, + IMX6Q_GPR5_ENET_TXCLK_SEL); + else + pr_err("failed to find fsl,imx6q-iomuxc-gpr regmap\n"); + } + clk_put(enet_ref); put_ptp_clk: clk_put(ptp_clk); diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index d4b5e527a7a3..eb65d48da0df 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -240,6 +240,7 @@ #define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0) #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) +#define IMX6Q_GPR5_ENET_TXCLK_SEL BIT(9) #define IMX6Q_GPR5_SATA_SW_PD BIT(10) #define IMX6Q_GPR5_SATA_SW_RST BIT(11) -- 2.17.1