From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1B67C433E0 for ; Thu, 18 Jun 2020 01:16:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ADA6721D80 for ; Thu, 18 Jun 2020 01:16:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1592442995; bh=wxagRCdDmLBVpwWsJ/YZCGc4NdGxBQAmrVSKQTkcppM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=ExHkLsRgjlX1SVYJVaZuljq9gzDNAZ3Qkwb8PRZNC9TGibQxiW7r1iMbKQ9A9Bqfs 24yeDDQJ3fer2nAoWbLydvquTIH+Td4jqiZAkr+t6WUeAfuD4iKXv7nPteHl3iYnqQ yeljXmzRB5rBif+FmaDOTuRer3YzLeG9V8HNk66w= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729593AbgFRBQd (ORCPT ); Wed, 17 Jun 2020 21:16:33 -0400 Received: from mail.kernel.org ([198.145.29.99]:43828 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728394AbgFRBOO (ORCPT ); Wed, 17 Jun 2020 21:14:14 -0400 Received: from sasha-vm.mshome.net (c-73-47-72-35.hsd1.nh.comcast.net [73.47.72.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 0459821D7B; Thu, 18 Jun 2020 01:14:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1592442853; bh=wxagRCdDmLBVpwWsJ/YZCGc4NdGxBQAmrVSKQTkcppM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=wIVu9cNQurT8hjqqVnuFPYpTTPcVjur4fVsYdg3TMj3buMmS24yDa2yGQ8nbVowWQ 2rse+h2UyrjGdyFs+WGqPshMOwpyh02WaZXZNTeB9QvAUdQMsB4odDiopF3cOmiTrh Px9Q7leFSamuEdb/SCI10rfAtDtkuQWlA4VTh2nQ= From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Tejas Patel , Jolly Shah , Stephen Boyd , Sasha Levin , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH AUTOSEL 5.7 284/388] clk: zynqmp: Fix divider2 calculation Date: Wed, 17 Jun 2020 21:06:21 -0400 Message-Id: <20200618010805.600873-284-sashal@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200618010805.600873-1-sashal@kernel.org> References: <20200618010805.600873-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tejas Patel [ Upstream commit b8c1049c68d634a412ed5980ae666ed7c8839305 ] zynqmp_get_divider2_val() calculates, divider value of type DIV2 clock, considering best possible combination of DIV1 and DIV2. To find best possible values of DIV1 and DIV2, DIV1's parent rate should be consider and not DIV2's parent rate since it would rate of div1 clock. Consider a below topology, out_clk->div2_clk->div1_clk->fixed_parent where out_clk = (fixed_parent/div1_clk) / div2_clk, so parent clock of div1_clk (i.e. out_clk) should be divided by div1_clk and div2_clk. Existing code divides parent rate of div2_clk's clock instead of div1_clk's parent rate, which is wrong. Fix the same by considering div1's parent clock rate. Fixes: 4ebd92d2e228 ("clk: zynqmp: Fix divider calculation") Signed-off-by: Tejas Patel Signed-off-by: Jolly Shah Link: https://lkml.kernel.org/r/1583185843-20707-3-git-send-email-jolly.shah@xilinx.com Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin --- drivers/clk/zynqmp/divider.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index 4be2cc76aa2e..9bc4f9409aea 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -111,23 +111,30 @@ static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw, static void zynqmp_get_divider2_val(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate, struct zynqmp_clk_divider *divider, int *bestdiv) { int div1; int div2; long error = LONG_MAX; - struct clk_hw *parent_hw = clk_hw_get_parent(hw); - struct zynqmp_clk_divider *pdivider = to_zynqmp_clk_divider(parent_hw); + unsigned long div1_prate; + struct clk_hw *div1_parent_hw; + struct clk_hw *div2_parent_hw = clk_hw_get_parent(hw); + struct zynqmp_clk_divider *pdivider = + to_zynqmp_clk_divider(div2_parent_hw); if (!pdivider) return; + div1_parent_hw = clk_hw_get_parent(div2_parent_hw); + if (!div1_parent_hw) + return; + + div1_prate = clk_hw_get_rate(div1_parent_hw); *bestdiv = 1; for (div1 = 1; div1 <= pdivider->max_div;) { for (div2 = 1; div2 <= divider->max_div;) { - long new_error = ((parent_rate / div1) / div2) - rate; + long new_error = ((div1_prate / div1) / div2) - rate; if (abs(new_error) < abs(error)) { *bestdiv = div2; @@ -192,7 +199,7 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, */ if (div_type == TYPE_DIV2 && (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { - zynqmp_get_divider2_val(hw, rate, *prate, divider, &bestdiv); + zynqmp_get_divider2_val(hw, rate, divider, &bestdiv); } if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac) -- 2.25.1