From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD1AFC433DF for ; Thu, 18 Jun 2020 02:51:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7578420776 for ; Thu, 18 Jun 2020 02:51:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1592448691; bh=OIkYKz3Teuu888niQkYcJHwn7SaAQqASF6j8tkUdRrw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=bWooobb7LToS/bH4KQIDmX6TlfsESUT5GOa6Po0J/Dv+vkmqoT1Cnxm87MwHk9yrB RFenA0SNZrozzw6FKXunBXSGjOjlgAs/bacXjBTvezNIODn3DqyqcsH/CcxzSYtYOT jLyVNcxcE4Rr9UkTzNHOD4UenD3sJ1muUDqPvXzw= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727989AbgFRBI7 (ORCPT ); Wed, 17 Jun 2020 21:08:59 -0400 Received: from mail.kernel.org ([198.145.29.99]:34744 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727911AbgFRBIs (ORCPT ); Wed, 17 Jun 2020 21:08:48 -0400 Received: from sasha-vm.mshome.net (c-73-47-72-35.hsd1.nh.comcast.net [73.47.72.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id BEBE021D7A; Thu, 18 Jun 2020 01:08:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1592442527; bh=OIkYKz3Teuu888niQkYcJHwn7SaAQqASF6j8tkUdRrw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ORZCshixEbxl+1pA6bA58N5Nda1/zN1MXq1YtQwP4/8FNM9FC8/tJb+EC3HQcSVYB Sub/QzcR+dzp44uWho/ajWMionBagu0+grJzwEwhx8mixRQoBzs/GERWOM+TqrxYO5 60SwCaBNW2ceT0rhKiquF5ZiFn+TjQvZT1cWVWNE= From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Jim Quinlan , Lorenzo Pieralisi , Florian Fainelli , Nicolas Saenz Julienne , Sasha Levin , bcm-kernel-feedback-list@broadcom.com, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org Subject: [PATCH AUTOSEL 5.7 031/388] PCI: brcmstb: Fix window register offset from 4 to 8 Date: Wed, 17 Jun 2020 21:02:08 -0400 Message-Id: <20200618010805.600873-31-sashal@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200618010805.600873-1-sashal@kernel.org> References: <20200618010805.600873-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Jim Quinlan [ Upstream commit 077a4fa92a615a4d0f86eae68d777b9dd5e5a95b ] The outbound memory window registers were being referenced with an incorrect stride offset. This probably wasn't noticed previously as there was likely only one such window employed. Link: https://lore.kernel.org/r/20200507201544.43432-3-james.quinlan@broadcom.com Fixes: c0452137034b ("PCI: brcmstb: Add Broadcom STB PCIe host controller driver") Signed-off-by: Jim Quinlan Signed-off-by: Lorenzo Pieralisi Acked-by: Florian Fainelli Acked-by: Nicolas Saenz Julienne Signed-off-by: Sasha Levin --- drivers/pci/controller/pcie-brcmstb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index 6d79d14527a6..c9ecc4d639c1 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -54,11 +54,11 @@ #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c #define PCIE_MEM_WIN0_LO(win) \ - PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4) + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 8) #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010 #define PCIE_MEM_WIN0_HI(win) \ - PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4) + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 8) #define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c #define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f -- 2.25.1