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Fri, 19 Jun 2020 10:46:43 +0000 Date: Fri, 19 Jun 2020 18:45:35 +0800 From: Jisheng Zhang To: Will Deacon , Robin Murphy , Mark Rutland , Catalin Marinas Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] arm64: perf: add support for Cortex-A75 Message-ID: <20200619184535.44835b99@xhacker.debian> In-Reply-To: <20200619184423.5e61a838@xhacker.debian> References: <20200619184423.5e61a838@xhacker.debian> X-Mailer: Claws Mail 3.17.5 (GTK+ 2.24.32; x86_64-pc-linux-gnu) Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-ClientProxiedBy: TYBP286CA0040.JPNP286.PROD.OUTLOOK.COM (2603:1096:404:10a::28) To DM6PR03MB3580.namprd03.prod.outlook.com (2603:10b6:5:b2::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from xhacker.debian (124.74.246.114) by TYBP286CA0040.JPNP286.PROD.OUTLOOK.COM (2603:1096:404:10a::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3109.22 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: 4JKUWlsoOUOMglmFNkuRoe7YAAU60EnMAFgX5fBV2FhTOxPPxv+ulhtr6K98nbqawHg1NF140VWhgJYL6F+lN212b/RtSVe3kaCjaQODG24oOPNdVjtcOnYqAqJio35nPzhrWYGRGiFNRWa5fPLn5K9ummkCnHlXTUTCNoKl36G7ar0ov1K2B0UCn2nda7eG2QdhMvN349P+1V7WOAUqJI5tje0reyvXgTQ0btiW0dGDrXFf3+QeJ/52RF8IWkHaP6xsn+pAjv9Tcq2Yx+hfXVuwStV6LO+vbbacRuYe6PDMiHTNnd58fWa64XhPeTIuEEkFqTssvLE2LPW6+68vmk8zLQLDfPA/PM+XYpJIK8ivJ2ZZIQogEgI/UL3tRGjicAr6JWfrhrGYg+AOtZN4TbzEh618GMQ+lOGnm2vBuJpSS1yO3cnk7H870E2l4DunQKTywD8Bca9b50v66AQDWpw/E7zFWPBireBGnqyCeqKojld1BpAF1lmPKT86a+e7 X-OriginatorOrg: synaptics.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2871fc6c-c7d9-4473-e809-08d8143e0e58 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2020 10:46:43.4930 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 335d1fbc-2124-4173-9863-17e7051a2a0e X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: o+fQp+zkrvxf4AKqo/se3zfCRg22phKSA5CJQZvWfPQlTLBtmNVvqIrRmI5DWMha/PXK2cfd3a4VUSmu7g/q/g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR03MB3481 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Cortex-A75 uses some implementation defined perf events. This patch sets up the necessary mapping for Cortex-A75. Mappings are based on Cortex-A75 TRM r3p1, section C2.3 PMU Events (pages C2-578 to C2-586). Signed-off-by: Jisheng Zhang --- arch/arm64/kernel/perf_event.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 743affbe0cca..55e1d75af708 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -123,6 +123,21 @@ static const unsigned armv8_a73_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR, }; +static const unsigned armv8_a75_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] = { + PERF_CACHE_MAP_ALL_UNSUPPORTED, + + [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD, + [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD, + [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR, + [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR, + + + [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD, + [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR, +}; + static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] [PERF_COUNT_HW_CACHE_OP_MAX] [PERF_COUNT_HW_CACHE_RESULT_MAX] = { @@ -940,6 +955,11 @@ static int armv8_a73_map_event(struct perf_event *event) return __armv8_pmuv3_map_event(event, NULL, &armv8_a73_perf_cache_map); } +static int armv8_a75_map_event(struct perf_event *event) +{ + return __armv8_pmuv3_map_event(event, NULL, &armv8_a75_perf_cache_map); +} + static int armv8_thunder_map_event(struct perf_event *event) { return __armv8_pmuv3_map_event(event, NULL, @@ -1101,7 +1121,7 @@ static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu) static int armv8_a75_pmu_init(struct arm_pmu *cpu_pmu) { return armv8_pmu_init(cpu_pmu, "armv8_cortex_a75", - armv8_pmuv3_map_event, NULL, NULL); + armv8_a75_map_event, NULL, NULL); } static int armv8_a76_pmu_init(struct arm_pmu *cpu_pmu) -- 2.27.0