Re: [PATCH v2 1/1] clk: qcom: gcc-msm8994: Add missing clocks, resets and GDSCs

[Bjorn Andersson <bjorn.andersson@linaro.org>]

On Mon 22 Jun 02:18 PDT 2020, Konrad Dybcio wrote:

> changes since v1:
> - refrain from reordering defines in the header

The changelog goes after '---' below.

> 
> This change adds GDSCs, resets and most of the missing
> clocks to the msm8994 GCC driver. The remaining ones
> are of local_vote_clk and gate_clk type, which are not
> yet supported upstream. Also reorder them to match the
> original downstream driver.
> 
> Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
> ---
>  drivers/clk/qcom/gcc-msm8994.c               | 388 ++++++++++++++++++-
>  include/dt-bindings/clock/qcom,gcc-msm8994.h |  36 ++
>  2 files changed, 423 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c
> index b7fc8c7ba195..144d2ba7a9be 100644
> --- a/drivers/clk/qcom/gcc-msm8994.c
> +++ b/drivers/clk/qcom/gcc-msm8994.c
> @@ -20,6 +20,7 @@
>  #include "clk-rcg.h"
>  #include "clk-branch.h"
>  #include "reset.h"
> +#include "gdsc.h"
>  
>  enum {
>  	P_XO,
> @@ -1772,6 +1773,32 @@ static struct clk_branch gcc_gp3_clk = {
>  	},
>  };
>  
> +static struct clk_branch gcc_lpass_q6_axi_clk = {
> +	.halt_reg = 0x0280,
> +	.clkr = {
> +		.enable_reg = 0x0280,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data)
> +		{
> +			.name = "gcc_lpass_q6_axi_clk",
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
> +	.halt_reg = 0x0284,
> +	.clkr = {
> +		.enable_reg = 0x0284,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data)
> +		{
> +			.name = "gcc_mss_q6_bimc_axi_clk",
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
>  static struct clk_branch gcc_pcie_0_aux_clk = {
>  	.halt_reg = 0x1ad4,
>  	.clkr = {
> @@ -1790,6 +1817,32 @@ static struct clk_branch gcc_pcie_0_aux_clk = {
>  	},
>  };
>  
> +static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
> +	.halt_reg = 0x1ad0,
> +	.clkr = {
> +		.enable_reg = 0x1ad0,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data)
> +		{
> +			.name = "gcc_pcie_0_cfg_ahb_clk",
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
> +	.halt_reg = 0x1acc,
> +	.clkr = {
> +		.enable_reg = 0x1acc,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data)
> +		{
> +			.name = "gcc_pcie_0_mstr_axi_clk",
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
>  static struct clk_branch gcc_pcie_0_pipe_clk = {
>  	.halt_reg = 0x1ad8,
>  	.halt_check = BRANCH_HALT_DELAY,
> @@ -1809,6 +1862,20 @@ static struct clk_branch gcc_pcie_0_pipe_clk = {
>  	},
>  };
>  
> +static struct clk_branch gcc_pcie_0_slv_axi_clk = {
> +	.halt_reg = 0x1ac8,
> +	.halt_check = BRANCH_HALT_DELAY,
> +	.clkr = {
> +		.enable_reg = 0x1ac8,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data)
> +		{
> +			.name = "gcc_pcie_0_slv_axi_clk",
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
>  static struct clk_branch gcc_pcie_1_aux_clk = {
>  	.halt_reg = 0x1b54,
>  	.clkr = {
> @@ -1827,6 +1894,32 @@ static struct clk_branch gcc_pcie_1_aux_clk = {
>  	},
>  };
>  
> +static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
> +	.halt_reg = 0x1b54,
> +	.clkr = {
> +		.enable_reg = 0x1b54,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data)
> +		{
> +			.name = "gcc_pcie_1_cfg_ahb_clk",
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
> +	.halt_reg = 0x1b50,
> +	.clkr = {
> +		.enable_reg = 0x1b50,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data)
> +		{
> +			.name = "gcc_pcie_1_mstr_axi_clk",
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
>  static struct clk_branch gcc_pcie_1_pipe_clk = {
>  	.halt_reg = 0x1b58,
>  	.halt_check = BRANCH_HALT_DELAY,
> @@ -1846,6 +1939,19 @@ static struct clk_branch gcc_pcie_1_pipe_clk = {
>  	},
>  };
>  
> +static struct clk_branch gcc_pcie_1_slv_axi_clk = {
> +	.halt_reg = 0x1b48,
> +	.clkr = {
> +		.enable_reg = 0x1b48,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data)
> +		{
> +			.name = "gcc_pcie_1_slv_axi_clk",
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
>  static struct clk_branch gcc_pdm2_clk = {
>  	.halt_reg = 0x0ccc,
>  	.clkr = {
> @@ -1864,6 +1970,19 @@ static struct clk_branch gcc_pdm2_clk = {
>  	},
>  };
>  
> +static struct clk_branch gcc_pdm_ahb_clk = {
> +	.halt_reg = 0x0cc4,
> +	.clkr = {
> +		.enable_reg = 0x0cc4,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data)
> +		{
> +			.name = "gcc_pdm_ahb_clk",
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
>  static struct clk_branch gcc_sdcc1_apps_clk = {
>  	.halt_reg = 0x04c4,
>  	.clkr = {
> @@ -1899,6 +2018,23 @@ static struct clk_branch gcc_sdcc1_ahb_clk = {
>  	},
>  };
>  
> +static struct clk_branch gcc_sdcc2_ahb_clk = {
> +	.halt_reg = 0x0508,
> +	.clkr = {
> +		.enable_reg = 0x0508,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data)
> +		{
> +			.name = "gcc_sdcc2_ahb_clk",
> +			.parent_names = (const char *[]){

Please convert these to use .parent_data instead.

Regards,
Bjorn