Re: [PATCH v33 02/21] x86/cpufeatures: x86/msr: Add Intel SGX Launch Control hardware bits

Sean Christopherson
2020-06-24T14:34:43Z

On Wed, Jun 24, 2020 at 03:04:34PM +0200, Borislav Petkov wrote:
> On Thu, Jun 18, 2020 at 01:08:24AM +0300, Jarkko Sakkinen wrote:
> > From: Sean Christopherson <sean.j.christopherson@intel.com>
> >
> > Add X86_FEATURE_SGX_LC, which informs whether or not the CPU supports SGX
> > Launch Control.
> >
> > Add MSR_IA32_SGXLEPUBKEYHASH{0, 1, 2, 3}, which when combined contain a
> > SHA256 hash of a 3072-bit RSA public key. SGX backed software packages, so
> > called enclaves, are always signed. All enclaves signed with the public key
> > are unconditionally allowed to initialize. [1]
> >
> > Add FEATURE_CONTROL_SGX_LE_WR bit of the feature control MSR, which informs
>
> LE_WR or LC_ENABLED?

It should be FEAT_CTL_SGX_LC_ENABLED, i.e. the actual code is correct. We
updated the #define to use the SDM name to be consistent with the other bits
and neglected to update the changelog.

Thanks!

> With that addressed:
>
> Reviewed-by: Borislav Petkov <bp@suse.de>
>
> --
> Regards/Gruss,
> Boris.
>
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