From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 939E0C433E0 for ; Fri, 26 Jun 2020 08:08:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6C3312076E for ; Fri, 26 Jun 2020 08:08:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729561AbgFZIIe (ORCPT ); Fri, 26 Jun 2020 04:08:34 -0400 Received: from 8bytes.org ([81.169.241.247]:50198 "EHLO theia.8bytes.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729146AbgFZIFt (ORCPT ); Fri, 26 Jun 2020 04:05:49 -0400 Received: by theia.8bytes.org (Postfix, from userid 1000) id 904D945B; Fri, 26 Jun 2020 10:05:48 +0200 (CEST) From: Joerg Roedel To: Joerg Roedel Cc: iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Suravee Suthikulpanit , Qian Cai , Joerg Roedel Subject: [PATCH v2 2/2] iommu/amd: Use 'unsigned long' for domain->pt_root Date: Fri, 26 Jun 2020 10:05:47 +0200 Message-Id: <20200626080547.24865-3-joro@8bytes.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200626080547.24865-1-joro@8bytes.org> References: <20200626080547.24865-1-joro@8bytes.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Joerg Roedel Using atomic64_t can be quite expensive, so use unsigned long instead. This is safe because the write becomes visible atomically. Signed-off-by: Joerg Roedel --- drivers/iommu/amd/amd_iommu_types.h | 2 +- drivers/iommu/amd/iommu.c | 15 +++++++++++++-- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h index 30a5d412255a..f6f102282dda 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -468,7 +468,7 @@ struct protection_domain { iommu core code */ spinlock_t lock; /* mostly used to lock the page table*/ u16 id; /* the domain id written to the device table */ - atomic64_t pt_root; /* pgtable root and pgtable mode */ + unsigned long pt_root; /* pgtable root and pgtable mode */ int glx; /* Number of levels for GCR3 table */ u64 *gcr3_tbl; /* Guest CR3 table */ unsigned long flags; /* flags to find out type of domain */ diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 5286ddcfc2f9..aec585f47646 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -156,7 +156,12 @@ static struct protection_domain *to_pdomain(struct iommu_domain *dom) static void amd_iommu_domain_get_pgtable(struct protection_domain *domain, struct domain_pgtable *pgtable) { - u64 pt_root = atomic64_read(&domain->pt_root); + unsigned long pt_root; + + /* Match the barrier in amd_iommu_domain_set_pt_root() */ + smp_rmb(); + + pt_root = READ_ONCE(domain->pt_root); pgtable->root = (u64 *)(pt_root & PAGE_MASK); pgtable->mode = pt_root & 7; /* lowest 3 bits encode pgtable mode */ @@ -164,7 +169,13 @@ static void amd_iommu_domain_get_pgtable(struct protection_domain *domain, static void amd_iommu_domain_set_pt_root(struct protection_domain *domain, u64 root) { - atomic64_set(&domain->pt_root, root); + WRITE_ONCE(domain->pt_root, root); + + /* + * The new value needs to be gobally visible in case pt_root gets + * cleared, so that the page-table can be safely freed. + */ + smp_wmb(); } static void amd_iommu_domain_clr_pt_root(struct protection_domain *domain) -- 2.27.0