From: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: "Stephen Boyd" <sboyd@kernel.org>,
"Andreas Färber" <afaerber@suse.de>,
"Rob Herring" <robh+dt@kernel.org>,
"Michael Turquette" <mturquette@baylibre.com>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-actions@lists.infradead.org
Subject: Re: [PATCH v2 1/6] clk: actions: Fix h_clk for Actions S500 SoC
Date: Fri, 26 Jun 2020 18:49:41 +0300 [thread overview]
Message-ID: <20200626154941.GA6611@BV030612LT> (raw)
In-Reply-To: <20200626134541.GB8333@Mani-XPS-13-9360>
On Fri, Jun 26, 2020 at 07:15:41PM +0530, Manivannan Sadhasivam wrote:
> On Wed, Jun 24, 2020 at 08:47:52PM +0300, Cristian Ciocaltea wrote:
> > The h_clk clock in the Actions Semi S500 SoC clock driver has an
> > invalid parent. Replace with the correct one.
> >
> > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>
> You should add fixes tag for this patch and it needs to be backported as well.
>
> Thanks,
> Mani
Right, I added the tag:
Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC")
Thanks,
Cristi
>
> > ---
> > drivers/clk/actions/owl-s500.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c
> > index e2007ac4d235..0eb83a0b70bc 100644
> > --- a/drivers/clk/actions/owl-s500.c
> > +++ b/drivers/clk/actions/owl-s500.c
> > @@ -183,7 +183,7 @@ static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
> > static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
> >
> > /* divider clocks */
> > -static OWL_DIVIDER(h_clk, "h_clk", "ahbprevdiv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
> > +static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
> > static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0);
> >
> > /* factor clocks */
> > --
> > 2.27.0
> >
next prev parent reply other threads:[~2020-06-26 15:49 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-24 17:47 [PATCH v2 0/6] Add RMU and DMAC/GPIO clock support for Actions Semi S500 SoCs Cristian Ciocaltea
2020-06-24 17:47 ` [PATCH v2 1/6] clk: actions: Fix h_clk for Actions S500 SoC Cristian Ciocaltea
2020-06-26 13:45 ` Manivannan Sadhasivam
2020-06-26 15:49 ` Cristian Ciocaltea [this message]
2020-06-24 17:47 ` [PATCH v2 2/6] dt-bindings: clock: Add APB, DMAC, GPIO bindings " Cristian Ciocaltea
[not found] ` <159303816030.62212.1603754983340876289@swboyd.mtv.corp.google.com>
2020-06-25 12:50 ` Cristian Ciocaltea
2020-06-24 17:47 ` [PATCH v2 3/6] clk: actions: Add APB, DMAC, GPIO clock support " Cristian Ciocaltea
2020-06-24 17:47 ` [PATCH v2 4/6] dt-bindings: reset: Add binding constants for Actions S500 RMU Cristian Ciocaltea
2020-06-26 12:14 ` Philipp Zabel
2020-06-24 17:47 ` [PATCH v2 5/6] clk: actions: Add Actions S500 SoC Reset Management Unit support Cristian Ciocaltea
2020-06-26 13:52 ` Manivannan Sadhasivam
2020-06-24 17:47 ` [PATCH v2 6/6] MAINTAINERS: Add reset binding entry for Actions Semi Owl SoCs Cristian Ciocaltea
2020-06-26 13:54 ` Manivannan Sadhasivam
2020-06-26 15:58 ` Cristian Ciocaltea
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