From: Rob Herring <robh@kernel.org>
To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>,
Vinod Koul <vkoul@kernel.org>,
devicetree@vger.kernel.org,
Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>,
Michal Simek <michal.simek@xilinx.com>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v9 1/3] dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHY
Date: Mon, 29 Jun 2020 16:30:11 -0600 [thread overview]
Message-ID: <20200629223011.GA3074548@bogus> (raw)
In-Reply-To: <20200629120054.29338-2-laurent.pinchart@ideasonboard.com>
On Mon, 29 Jun 2020 15:00:52 +0300, Laurent Pinchart wrote:
> From: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
>
> Add DT bindings for the Xilinx ZynqMP PHY. ZynqMP SoCs have a High Speed
> Processing System Gigabit Transceiver which provides PHY capabilities to
> USB, SATA, PCIE, Display Port and Ehernet SGMII controllers.
>
> Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
> Changes since v8:
>
> - Rebase on phy/next
>
> Changes since v7:
>
> - Switch to GPL-2.0-only OR BSD-2-Clause
>
> Changes since v6:
>
> - Fixed specification of compatible-dependent xlnx,tx-termination-fix
> property
> - Dropped status property from example
> - Use 4 spaces to indent example
>
> Changes since v5:
>
> - Document clocks and clock-names properties
> - Document resets and reset-names properties
> - Replace subnodes with an additional entry in the PHY cells
> - Drop lane frequency PHY cell, replaced by reference clock phandle
> - Convert bindings to YAML
> - Reword the subject line
> - Drop Rob's R-b as the bindings have significantly changed
> - Drop resets and reset-names properties
> ---
> .../bindings/phy/xlnx,zynqmp-psgtr.yaml | 105 ++++++++++++++++++
> include/dt-bindings/phy/phy.h | 1 +
> 2 files changed, 106 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.example.dt.yaml: example-0: phy@fd400000:reg:0: [0, 4248829952, 0, 262144] is too long
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.example.dt.yaml: example-0: phy@fd400000:reg:1: [0, 4248633344, 0, 4096] is too long
See https://patchwork.ozlabs.org/patch/1319269
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure dt-schema is up to date:
pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade
Please check and re-submit.
next prev parent reply other threads:[~2020-06-29 22:30 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-29 12:00 [PATCH v9 0/3] phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver Laurent Pinchart
2020-06-29 12:00 ` [PATCH v9 1/3] dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHY Laurent Pinchart
2020-06-29 22:30 ` Rob Herring [this message]
2020-07-01 13:33 ` Laurent Pinchart
2020-07-01 23:04 ` Rob Herring
2020-06-29 12:00 ` [PATCH v9 2/3] phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver Laurent Pinchart
2020-06-29 12:00 ` [PATCH v9 3/3] arm64: dts: zynqmp: Add GTR transceivers Laurent Pinchart
2020-06-29 13:19 ` [PATCH v9 0/3] phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver Vinod Koul
2020-06-29 13:49 ` Laurent Pinchart
2020-07-08 8:32 ` Michal Simek
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