From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B663C433E0 for ; Tue, 30 Jun 2020 00:11:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7A21B20781 for ; Tue, 30 Jun 2020 00:11:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="A+ghUT/H" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728678AbgF3ALD (ORCPT ); Mon, 29 Jun 2020 20:11:03 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:8838 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726182AbgF3AK5 (ORCPT ); Mon, 29 Jun 2020 20:10:57 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 29 Jun 2020 17:10:08 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 29 Jun 2020 17:10:57 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 29 Jun 2020 17:10:57 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 30 Jun 2020 00:10:52 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 30 Jun 2020 00:10:51 +0000 Received: from vdumpa-ubuntu.nvidia.com (Not Verified[172.17.173.140]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Mon, 29 Jun 2020 17:10:51 -0700 From: Krishna Reddy CC: , , , , , , , , , , , , , , , , , Krishna Reddy Subject: [PATCH v8 2/3] dt-bindings: arm-smmu: Add binding for Tegra194 SMMU Date: Mon, 29 Jun 2020 17:10:50 -0700 Message-ID: <20200630001051.12350-3-vdumpa@nvidia.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200630001051.12350-1-vdumpa@nvidia.com> References: <20200630001051.12350-1-vdumpa@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1593475808; bh=Jc+XyeC88tqkNN/9PiqUq0uk5O5JxUm8Rkp1FWBteWQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=A+ghUT/Hr2fGTMTLyRcX9YvnCJO51ep5kUYiXbkSKJvRxBwsdktFn6J72G+ISD8c4 64XGgD9xmgLOQwyBsrzE67oR/TZSZK3GRvO03foy0ypGW/Cf1iZnKLYKdqF9YjMsWF duxG2OvkRJGFR3nj7Di0qonZPNf3RH8VxcNGlBdXZ1Ncagrdxe6zJvjUVnnvRZ0vSz 2/lRuEACCVV7z9YPFUoNIzsIyBBWbeEbLklM3Epwi4qPE8c0oyd09KXIGD/zc73E4k WyPGMgRybgtmqaWBpxv0TDfj0ajVoYv6aUfDK29k8gZSSuIXyCyuVg5qbZqEgUgTkl YSDvfgQNTz1gw== To: unlisted-recipients:; (no To-header on input) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add binding for NVIDIA's Tegra194 SoC SMMU topology that is based on ARM MMU-500. Signed-off-by: Krishna Reddy --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Docume= ntation/devicetree/bindings/iommu/arm,smmu.yaml index d7ceb4c34423b..5b2586ac715ed 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -38,6 +38,11 @@ properties: - qcom,sc7180-smmu-500 - qcom,sdm845-smmu-500 - const: arm,mmu-500 + - description: NVIDIA SoCs that use more than one "arm,mmu-500" + items: + - enum: + - nvdia,tegra194-smmu + - const: arm,mmu-500 - items: - const: arm,mmu-500 - const: arm,smmu-v2 --=20 2.26.2