[PATCH 0/2] add Intel Max10 BMC chip support

Xu Yilun
2020-07-13T04:39:43Z

This patchset add basic functions for Intel Max10 BMC chip.
Patch #1 implements the main feature.
Patch #2 is a fix for the HW issue lies in the "SPI Slave to Avalon Master
bridge" IP block, which is used for communication between host and the BMC
chip.

Matthew Gerlach (1):
mfd: intel-m10-bmc: start with the last SOP on phy rx buffer parsing

Xu Yilun (1):
mfd: intel-m10-bmc: add Max10 BMC chip support for Intel FPGA PAC

.../ABI/testing/sysfs-driver-intel-m10-bmc | 15 +
drivers/mfd/Kconfig | 13 +
drivers/mfd/Makefile | 3 +
drivers/mfd/intel-m10-bmc-main.c | 176 ++++
drivers/mfd/intel-spi-avmm.c | 904 +++++++++++++++++++++
drivers/mfd/intel-spi-avmm.h | 35 +
include/linux/mfd/intel-m10-bmc.h | 57 ++
7 files changed, 1203 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-driver-intel-m10-bmc
create mode 100644 drivers/mfd/intel-m10-bmc-main.c
create mode 100644 drivers/mfd/intel-spi-avmm.c
create mode 100644 drivers/mfd/intel-spi-avmm.h
create mode 100644 include/linux/mfd/intel-m10-bmc.h

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2.7.4