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[216.228.112.21]) by smtp.gmail.com with ESMTPSA id nk22sm912733pjb.51.2020.07.16.16.20.28 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 16 Jul 2020 16:20:28 -0700 (PDT) Date: Thu, 16 Jul 2020 16:20:02 -0700 From: Nicolin Chen To: Arnaud Ferraris Cc: alsa-devel@alsa-project.org, Timur Tabi , Xiubo Li , Fabio Estevam , Shengjiu Wang , Liam Girdwood , Mark Brown , linux-kernel@vger.kernel.org, kernel@collabora.com Subject: Re: [PATCH v2 1/2] ASoC: fsl_asrc: make sure the input and output clocks are different Message-ID: <20200716232000.GA27246@Asurada-Nvidia> References: <20200716145201.186270-1-arnaud.ferraris@collabora.com> <20200716151352.193451-1-arnaud.ferraris@collabora.com> <20200716151352.193451-2-arnaud.ferraris@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200716151352.193451-2-arnaud.ferraris@collabora.com> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jul 16, 2020 at 05:13:52PM +0200, Arnaud Ferraris wrote: > The current clock selection algorithm might select the same clock for > both input and output. This can happen when, for instance, the output > sample rate is a multiple of the input rate. What's the issue when selecting the same clock source for both input and output? Please explain it in the commit logs. > This patch makes sure it always selects distinct input and output > clocks. > > Signed-off-by: Arnaud Ferraris > --- > sound/soc/fsl/fsl_asrc.c | 11 ++++++----- > 1 file changed, 6 insertions(+), 5 deletions(-) > > diff --git a/sound/soc/fsl/fsl_asrc.c b/sound/soc/fsl/fsl_asrc.c > index 02c81d2e34ad..6d43cab6c885 100644 > --- a/sound/soc/fsl/fsl_asrc.c > +++ b/sound/soc/fsl/fsl_asrc.c > @@ -608,8 +608,8 @@ static void fsl_asrc_select_clk(struct fsl_asrc_priv *asrc_priv, > { > struct fsl_asrc_pair_priv *pair_priv = pair->private; > struct asrc_config *config = pair_priv->config; > - int rate[2], select_clk[2]; /* Array size 2 means IN and OUT */ > - int clk_rate, clk_index; > + int rate[2], select_clk[2], clk_index[2]; /* Array size 2 means IN and OUT */ > + int clk_rate; > int i = 0, j = 0; > > rate[IN] = in_rate; > @@ -618,11 +618,12 @@ static void fsl_asrc_select_clk(struct fsl_asrc_priv *asrc_priv, > /* Select proper clock source for internal ratio mode */ > for (j = 0; j < 2; j++) { > for (i = 0; i < ASRC_CLK_MAP_LEN; i++) { > - clk_index = asrc_priv->clk_map[j][i]; > - clk_rate = clk_get_rate(asrc_priv->asrck_clk[clk_index]); > + clk_index[j] = asrc_priv->clk_map[j][i]; > + clk_rate = clk_get_rate(asrc_priv->asrck_clk[clk_index[j]]); > /* Only match a perfect clock source with no remainder */ Better to update the comments here as there's a new condition. > if (clk_rate != 0 && (clk_rate / rate[j]) <= 1024 && > - (clk_rate % rate[j]) == 0) > + (clk_rate % rate[j]) == 0 && > + (j == 0 || clk_index[j] != clk_index[j-1])) clk_index[j - 1]