Re: [PATCH 11/19] clk: at91: clk-generated: pass the id of changeable parent at registration

Codrin.Ciubotariu
2020-07-16T16:57:24Z

Hi Claudiu,

On 15.07.2020 14:24, Claudiu Beznea wrote:
> Pass the ID of changeable parent at registration. This will allow
> the scalability of this clock driver with regards to the changeable
> parent ID for versions of this IP where changeable parent is not the
> last one in the parents list (e.g. SAMA7G5). In
> clk_generated_best_diff() the *best_diff variable is check against
> tmp_diff variable using ">=" operator instead of ">" so that in case
> the requested frequency could be obtained using fix parents + gck
> dividers but the clock also supports changeable parent to be able
> to force the usage of the changeable parent.

This is a great feature!

>
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
> drivers/clk/at91/clk-generated.c | 26 ++++++++++++++------------
> drivers/clk/at91/dt-compat.c | 8 +++++---
> drivers/clk/at91/pmc.h | 4 ++--
> drivers/clk/at91/sam9x60.c | 3 +--
> drivers/clk/at91/sama5d2.c | 31 +++++++++++++++----------------
> 5 files changed, 37 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c
> index 2448bdc63425..f9ca04c97128 100644
> --- a/drivers/clk/at91/clk-generated.c
> +++ b/drivers/clk/at91/clk-generated.c
> @@ -18,8 +18,6 @@
>
> #define GENERATED_MAX_DIV 255
>
> -#define GCK_INDEX_DT_AUDIO_PLL 5
> -
> struct clk_generated {
> struct clk_hw hw;
> struct regmap *regmap;
> @@ -29,7 +27,7 @@ struct clk_generated {
> u32 gckdiv;
> const struct clk_pcr_layout *layout;
> u8 parent_id;
> - bool audio_pll_allowed;
> + int chg_pid;
> };
>
> #define to_clk_generated(hw) \
> @@ -109,7 +107,7 @@ static void clk_generated_best_diff(struct clk_rate_request *req,
> tmp_rate = parent_rate / div;
> tmp_diff = abs(req->rate - tmp_rate);
>
> - if (*best_diff < 0 || *best_diff > tmp_diff) {
> + if (*best_diff < 0 || *best_diff >= tmp_diff) {
> *best_rate = tmp_rate;
> *best_diff = tmp_diff;
> req->best_parent_rate = parent_rate;
> @@ -129,7 +127,10 @@ static int clk_generated_determine_rate(struct clk_hw *hw,
> int i;
> u32 div;
>
> - for (i = 0; i < clk_hw_get_num_parents(hw) - 1; i++) {
> + for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
> + if (gck->chg_pid == i)
> + continue;
> +

One thing that the previous loop was preventing was to not allow other
gcks take clk_hw_get_num_parents(hw) - 1 as a parent. So the audio pll
(last one) was reserved for the gck of the audio peripherals only. With
this change, any peripheral can use chg_pid as a parent, preventing thus
its correct use by the peripherals that can actually need and change the
rate of chg_pid.

> parent = clk_hw_get_parent_by_index(hw, i);
> if (!parent)
> continue;
> @@ -161,10 +162,10 @@ static int clk_generated_determine_rate(struct clk_hw *hw,
> * that the only clks able to modify gck rate are those of audio IPs.
> */

The above comment should be updated.

>
> - if (!gck->audio_pll_allowed)
> + if (gck->chg_pid < 0)
> goto end;

Best regards,
Codrin