From: kan.liang@linux.intel.com
To: peterz@infradead.org, acme@redhat.com, mingo@kernel.org,
linux-kernel@vger.kernel.org
Cc: jolsa@kernel.org, eranian@google.com,
alexander.shishkin@linux.intel.com, ak@linux.intel.com,
Kan Liang <kan.liang@linux.intel.com>
Subject: [PATCH V6 08/14] perf/x86: Add a macro for RDPMC offset of fixed counters
Date: Fri, 17 Jul 2020 07:05:48 -0700 [thread overview]
Message-ID: <20200717140554.22863-9-kan.liang@linux.intel.com> (raw)
In-Reply-To: <20200717140554.22863-1-kan.liang@linux.intel.com>
From: Kan Liang <kan.liang@linux.intel.com>
The RDPMC base offset of fixed counters is hard-code. Use a meaningful
name to replace the magic number to improve the readability of the code.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
arch/x86/events/core.c | 3 ++-
arch/x86/include/asm/perf_event.h | 3 +++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 8aa7da80f5d6..ace21b133015 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -1158,7 +1158,8 @@ static inline void x86_assign_hw_event(struct perf_event *event,
hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 +
(idx - INTEL_PMC_IDX_FIXED);
- hwc->event_base_rdpmc = (idx - INTEL_PMC_IDX_FIXED) | 1<<30;
+ hwc->event_base_rdpmc = (idx - INTEL_PMC_IDX_FIXED) |
+ INTEL_PMC_FIXED_RDPMC_BASE;
break;
default:
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 8870eb1c3b17..84bfb9d1f948 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -196,6 +196,9 @@ struct x86_pmu_capability {
* Fixed-purpose performance events:
*/
+/* RDPMC offset for Fixed PMCs */
+#define INTEL_PMC_FIXED_RDPMC_BASE (1 << 30)
+
/*
* All the fixed-mode PMCs are configured via this single MSR:
*/
--
2.17.1
next prev parent reply other threads:[~2020-07-17 14:08 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-17 14:05 [PATCH V6 00/14] TopDown metrics support for Icelake kan.liang
2020-07-17 14:05 ` [PATCH V6 01/14] perf/x86: Use event_base_rdpmc for the RDPMC userspace support kan.liang
2020-07-17 14:05 ` [PATCH V6 02/14] perf/x86/intel: Name the global status bit in NMI handler kan.liang
2020-07-17 14:05 ` [PATCH V6 03/14] perf/x86/intel: Introduce the fourth fixed counter kan.liang
2020-07-20 16:20 ` Peter Zijlstra
2020-07-20 18:22 ` Liang, Kan
2020-07-17 14:05 ` [PATCH V6 04/14] perf/x86/intel: Move BTS index to 47 kan.liang
2020-07-17 14:05 ` [PATCH V6 05/14] perf/x86/intel: Fix the name of perf METRICS kan.liang
2020-07-17 14:05 ` [PATCH V6 06/14] perf/x86/intel: Use switch in intel_pmu_disable/enable_event kan.liang
2020-07-20 16:22 ` Peter Zijlstra
2020-07-20 19:02 ` Liang, Kan
2020-07-17 14:05 ` [PATCH V6 07/14] perf/x86/intel: Generic support for hardware TopDown metrics kan.liang
2020-07-20 17:41 ` Peter Zijlstra
2020-07-20 18:11 ` Liang, Kan
2020-07-21 9:43 ` Peter Zijlstra
2020-07-21 14:05 ` Liang, Kan
2020-07-21 14:25 ` peterz
2020-07-17 14:05 ` kan.liang [this message]
2020-07-17 14:05 ` [PATCH V6 09/14] perf/x86/intel: Support TopDown metrics on Ice Lake kan.liang
2020-07-21 12:40 ` Peter Zijlstra
2020-07-21 14:23 ` Liang, Kan
2020-07-21 14:31 ` peterz
2020-07-21 15:50 ` Liang, Kan
2020-07-21 17:38 ` Andi Kleen
2020-07-21 19:20 ` Peter Zijlstra
2020-07-17 14:05 ` [PATCH V6 10/14] perf/x86/intel: Support per-thread RDPMC TopDown metrics kan.liang
2020-07-17 14:05 ` [PATCH V6 11/14] perf/x86/intel: Disable sample-read the slots and metrics events kan.liang
2020-07-21 13:10 ` Peter Zijlstra
2020-07-21 16:07 ` Liang, Kan
2020-07-21 19:18 ` Peter Zijlstra
2020-07-22 19:26 ` Liang, Kan
2020-07-17 14:05 ` [PATCH V6 12/14] perf, tools, stat: Support new per thread TopDown metrics kan.liang
2020-07-17 14:05 ` [PATCH V6 13/14] perf, tools, stat: Check Topdown Metric group kan.liang
2020-07-17 14:05 ` [PATCH V6 14/14] perf, tools: Add documentation for topdown metrics kan.liang
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