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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id b21sm16520817pfb.45.2020.07.27.13.34.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jul 2020 13:34:39 -0700 (PDT) Date: Mon, 27 Jul 2020 14:34:36 -0600 From: Mathieu Poirier To: Wei Li Cc: leo.yan@linaro.org, Suzuki K Poulose , Mike Leach , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Kim Phillips , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Peter Zijlstra , Ingo Molnar , guohanjun@huawei.com Subject: Re: [PATCH v2 2/2] perf tools: ARM SPE code cleanup Message-ID: <20200727203436.GC2381376@xps15> References: <20200724071111.35593-1-liwei391@huawei.com> <20200724071111.35593-3-liwei391@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200724071111.35593-3-liwei391@huawei.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jul 24, 2020 at 03:11:11PM +0800, Wei Li wrote: > - Firstly, the function auxtrace_record__init() will be invoked only > once, the variable "arm_spe_pmus" will not be used afterwards, thus > we don't need to check "arm_spe_pmus" is NULL or not; > - Another reason is, even though SPE is micro-architecture dependent, > but so far it only supports "statistical-profiling-extension-v1" and > we have no chance to use multiple SPE's PMU events in Perf command. I find the above changelog somewhat out of touch with the patch itself. The only thing that is happening here is the removal of a useless check and a fix for a memory leak. Once again whether Arnaldo wants to make the changes by hand or not you may have to resubmit. Reviewed-by: Mathieu Poirier > > So remove the useless check code to make it clear. > > Signed-off-by: Wei Li > --- > tools/perf/arch/arm/util/auxtrace.c | 9 ++++----- > 1 file changed, 4 insertions(+), 5 deletions(-) > > diff --git a/tools/perf/arch/arm/util/auxtrace.c b/tools/perf/arch/arm/util/auxtrace.c > index 28a5d0c18b1d..b187bddbd01a 100644 > --- a/tools/perf/arch/arm/util/auxtrace.c > +++ b/tools/perf/arch/arm/util/auxtrace.c > @@ -57,17 +57,15 @@ struct auxtrace_record > struct evsel *evsel; > bool found_etm = false; > struct perf_pmu *found_spe = NULL; > - static struct perf_pmu **arm_spe_pmus = NULL; > - static int nr_spes = 0; > + struct perf_pmu **arm_spe_pmus = NULL; > + int nr_spes = 0; > int i = 0; > > if (!evlist) > return NULL; > > cs_etm_pmu = perf_pmu__find(CORESIGHT_ETM_PMU_NAME); > - > - if (!arm_spe_pmus) > - arm_spe_pmus = find_all_arm_spe_pmus(&nr_spes, err); > + arm_spe_pmus = find_all_arm_spe_pmus(&nr_spes, err); > > evlist__for_each_entry(evlist, evsel) { > if (cs_etm_pmu && > @@ -84,6 +82,7 @@ struct auxtrace_record > } > } > } > + free(arm_spe_pmus); > > if (found_etm && found_spe) { > pr_err("Concurrent ARM Coresight ETM and SPE operation not currently supported\n"); > -- > 2.17.1 >