From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3122C433E1 for ; Tue, 4 Aug 2020 16:56:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ADDC522B42 for ; Tue, 4 Aug 2020 16:56:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mailerdienst.de header.i=@mailerdienst.de header.b="dIenpDED" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729801AbgHDQ4x (ORCPT ); Tue, 4 Aug 2020 12:56:53 -0400 Received: from mxwww.masterlogin.de ([95.129.51.220]:46224 "EHLO mxwww.masterlogin.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728247AbgHDQ4Y (ORCPT ); Tue, 4 Aug 2020 12:56:24 -0400 Received: from mxout1.routing.net (unknown [192.168.10.81]) by forward.mxwww.masterlogin.de (Postfix) with ESMTPS id 5467A96153; Tue, 4 Aug 2020 16:56:13 +0000 (UTC) Received: from mxbox3.masterlogin.de (unknown [192.168.10.78]) by mxout1.routing.net (Postfix) with ESMTP id 2D0FC402F8; Tue, 4 Aug 2020 16:56:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailerdienst.de; s=20200217; t=1596560173; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=P6cNEjRALO0TlHjFZLwAJkcxyJkEDRqVED41Xard7SE=; b=dIenpDEDIxH+p2CzkBrC4sjz/hiTVVg0J55RuLf39UDZWElo3qslZ+2d5jso+UTqcY1kT7 e2bSl1bDh/zSWqWOTj9L6U3KLHINflAIcfwHUHWzEPLmxG4cI/11YvlPTnai14zhUH1cRb atYymnuIdYYE8nwGeg5NGl7H3uLjL2c= Received: from localhost.localdomain (fttx-pool-217.61.144.119.bambit.de [217.61.144.119]) by mxbox3.masterlogin.de (Postfix) with ESMTPSA id 6B87F3601C7; Tue, 4 Aug 2020 16:56:12 +0000 (UTC) From: Frank Wunderlich To: linux-mediatek@lists.infradead.org Cc: Frank Wunderlich , Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jitao Shi Subject: [PATCH v4 5/6] drm/mediatek: dpi/dsi: change the getting possible_crtc way Date: Tue, 4 Aug 2020 18:55:54 +0200 Message-Id: <20200804165555.75159-7-linux@fw-web.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200804165555.75159-1-linux@fw-web.de> References: <20200804165555.75159-1-linux@fw-web.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Jitao Shi For current mediatek dsi encoder, its possible crtc is fixed in crtc 0, and mediatek dpi encoder's possible crtc is fixed in crtc 1. In some SoC the possible crtc is not fixed in this case, so call mtk_drm_find_possible_crtc_by_comp() to find out the correct possible crtc. Signed-off-by: Jitao Shi Signed-off-by: Frank Wunderlich Reviewed-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 3 ++- drivers/gpu/drm/mediatek/mtk_dsi.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index d4f0fb7ad312..e43977015843 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -608,7 +608,8 @@ static int mtk_dpi_bind(struct device *dev, struct device *master, void *data) drm_encoder_helper_add(&dpi->encoder, &mtk_dpi_encoder_helper_funcs); /* Currently DPI0 is fixed to be driven by OVL1 */ - dpi->encoder.possible_crtcs = BIT(1); + dpi->encoder.possible_crtcs = + mtk_drm_find_possible_crtc_by_comp(drm_dev, dpi->ddp_comp); ret = drm_bridge_attach(&dpi->encoder, dpi->bridge, NULL, 0); if (ret) { diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 270bf22c98fe..c31d9c12d4a9 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -892,7 +892,8 @@ static int mtk_dsi_create_conn_enc(struct drm_device *drm, struct mtk_dsi *dsi) * Currently display data paths are statically assigned to a crtc each. * crtc 0 is OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 */ - dsi->encoder.possible_crtcs = 1; + dsi->encoder.possible_crtcs = + mtk_drm_find_possible_crtc_by_comp(drm, dsi->ddp_comp); /* If there's a bridge, attach to it and let it create the connector */ if (dsi->bridge) { -- 2.25.1