From: Sean Christopherson <sean.j.christopherson@intel.com>
To: Wanpeng Li <kernellwp@gmail.com>
Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
Paolo Bonzini <pbonzini@redhat.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
Jim Mattson <jmattson@google.com>, Joerg Roedel <joro@8bytes.org>
Subject: Re: [PATCH v2 1/2] KVM: LAPIC: Return 0 when getting the tscdeadline timer if the lapic is hw disabled
Date: Thu, 13 Aug 2020 07:57:24 -0700 [thread overview]
Message-ID: <20200813145724.GE29439@linux.intel.com> (raw)
In-Reply-To: <1597213838-8847-1-git-send-email-wanpengli@tencent.com>
On Wed, Aug 12, 2020 at 02:30:37PM +0800, Wanpeng Li wrote:
> From: Wanpeng Li <wanpengli@tencent.com>
>
> Return 0 when getting the tscdeadline timer if the lapic is hw disabled.
It'd be helpful to reference the SDM for the general behavior of the MSR.
In other timer modes (LVT bit 18 = 0), the IA32_TSC_DEADLINE MSR reads
zero and writes are ignored.
I'd also vote to squash the two patches together, they really are paired
changes to match the architectural behavior.
Reviewed-by: Sean Christopherson <sean.j.christopherson@intel.com>
next prev parent reply other threads:[~2020-08-13 14:57 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-12 6:30 [PATCH v2 1/2] KVM: LAPIC: Return 0 when getting the tscdeadline timer if the lapic is hw disabled Wanpeng Li
2020-08-12 6:30 ` [PATCH v2 2/2] KVM: LAPIC: Guarantee the timer is in tsc-deadline mode when setting Wanpeng Li
2020-08-13 14:58 ` Sean Christopherson
2020-08-24 1:04 ` Wanpeng Li
2020-08-25 0:58 ` Sean Christopherson
2020-08-13 14:57 ` Sean Christopherson [this message]
2020-08-25 0:57 ` [PATCH v2 1/2] KVM: LAPIC: Return 0 when getting the tscdeadline timer if the lapic is hw disabled Sean Christopherson
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