From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE368C433E5 for ; Wed, 26 Aug 2020 02:47:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8C7F120737 for ; Wed, 26 Aug 2020 02:47:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="V/8DoIKF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726802AbgHZCro (ORCPT ); Tue, 25 Aug 2020 22:47:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34762 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726804AbgHZCrX (ORCPT ); Tue, 25 Aug 2020 22:47:23 -0400 Received: from mail-pl1-x644.google.com (mail-pl1-x644.google.com [IPv6:2607:f8b0:4864:20::644]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1EE18C0613ED for ; Tue, 25 Aug 2020 19:47:23 -0700 (PDT) Received: by mail-pl1-x644.google.com with SMTP id j11so193405plk.9 for ; Tue, 25 Aug 2020 19:47:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xwN4Lh5cIbYb5K/fWg1B1RhUro5At/hehYhhAFZFYDY=; b=V/8DoIKFqL1t3FLvYq8/l7xLxPfVGIXwJ1LprRG6Ar2GN7u5kw0eENVpp9WIff+g5p tJHoCSn/KU3XF7Xk4pqGb3wxgsKmqDycD915IA70H9fDm1IADy46q5Iuy+zDRBjO4d3O iAIaduDi8sTB7gwHCJEb/oUKdD8YkfREn5clE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xwN4Lh5cIbYb5K/fWg1B1RhUro5At/hehYhhAFZFYDY=; b=ufdrAghuNFCrHnmB5CSvOSoPa9jhZFjSSOSIF6xV4T6LFU/bf7cwYdgUL3wq6PMCjx yDvRUm/7AubrQAs+JIUIF1vmPlCPpqbnX0FqroJMu2RSCclkvKo8LNoMfYZzF7chws+G UrtXfgzzLYHKzGF7BakUuqqxlu9wagT/YrbOv1/SSupLQ33ux+MKN5uBmUK/vfIa8S8L SYsxPXOnzEORtiFyUyGNJRxqW+9tx5yVwRROgkXDwKxFxiWB40VcRlaTb8v4wUbmr1K7 hU4vtx356EYlQE5fgLTthykBTmFvLdWUhUa42VZcmLAOeMDJnSnWc2/wTkMm33p6wOgc PXIg== X-Gm-Message-State: AOAM532n1ChvsrkBi1v2ksF5p397k/MOrj0ws4YOUH0ChA1mgoTZm/R2 BhTTYQfer2uAJRHQipaKX0jFyw== X-Google-Smtp-Source: ABdhPJx0mwnpy4fyQKQX2Ne1wN9JaxPc5pzKLfpJbtO5TCBzMLsN0ZbIFFkIPYHWQi07PiNjgy8tRw== X-Received: by 2002:a17:90a:9503:: with SMTP id t3mr4143235pjo.171.1598410042690; Tue, 25 Aug 2020 19:47:22 -0700 (PDT) Received: from smtp.gmail.com ([2620:15c:202:1:3e52:82ff:fe6c:83ab]) by smtp.gmail.com with ESMTPSA id u65sm684381pfb.102.2020.08.25.19.47.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 19:47:22 -0700 (PDT) From: Stephen Boyd To: Kishon Vijay Abraham I , Vinod Koul Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Jeykumar Sankaran , Chandan Uddaraju , Vara Reddy , Tanmay Shah , Bjorn Andersson , Manu Gautam , Sandeep Maheswaram , Douglas Anderson , Sean Paul , Stephen Boyd , Jonathan Marek , Dmitry Baryshkov , Rob Clark Subject: [PATCH v1 8/9] clk: qcom: dispcc: Update DP clk ops for phy design Date: Tue, 25 Aug 2020 19:47:10 -0700 Message-Id: <20200826024711.220080-9-swboyd@chromium.org> X-Mailer: git-send-email 2.28.0.297.g1956fa8f8d-goog In-Reply-To: <20200826024711.220080-1-swboyd@chromium.org> References: <20200826024711.220080-1-swboyd@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The clk_rcg2_dp_determine_rate() function is used for the DP pixel clk. This function should return the rate that can be achieved by the pixel clk in 'struct clk_rate_request::rate' and match the logic similar to what is seen in clk_rcg2_dp_set_rate(). But that isn't the case. Instead the code merely bubbles the rate request up to the parent of the pixel clk and doesn't try to do a rational approximation of the rate that would be achieved by picking some m/n value for the RCG. Let's change this logic so that we can assume the parent clk frequency is fixed (it is because it's the VCO of the DP PLL that is configured based on the link rate) and so that we can calculate what the m/n value will be and adjust the req->rate appropriately. Cc: Jeykumar Sankaran Cc: Chandan Uddaraju Cc: Vara Reddy Cc: Tanmay Shah Cc: Bjorn Andersson Cc: Manu Gautam Cc: Sandeep Maheswaram Cc: Douglas Anderson Cc: Sean Paul Cc: Stephen Boyd Cc: Jonathan Marek Cc: Dmitry Baryshkov Cc: Rob Clark Signed-off-by: Stephen Boyd --- drivers/clk/qcom/clk-rcg2.c | 19 +++++++++++++------ drivers/clk/qcom/dispcc-sc7180.c | 3 --- 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 357159fe85b5..59a5a0f261f3 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -1182,14 +1182,21 @@ static int clk_rcg2_dp_set_rate_and_parent(struct clk_hw *hw, static int clk_rcg2_dp_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { - struct clk_rate_request parent_req = *req; - int ret; + struct clk_rcg2 *rcg = to_clk_rcg2(hw); + unsigned long num, den; + u64 tmp; - ret = __clk_determine_rate(clk_hw_get_parent(hw), &parent_req); - if (ret) - return ret; + /* Parent rate is a fixed phy link rate */ + rational_best_approximation(req->best_parent_rate, req->rate, + GENMASK(rcg->mnd_width - 1, 0), + GENMASK(rcg->mnd_width - 1, 0), &den, &num); + + if (!num || !den) + return -EINVAL; - req->best_parent_rate = parent_req.rate; + tmp = req->best_parent_rate * num; + do_div(tmp, den); + req->rate = tmp; return 0; } diff --git a/drivers/clk/qcom/dispcc-sc7180.c b/drivers/clk/qcom/dispcc-sc7180.c index 0a5d395bce93..f487515701e3 100644 --- a/drivers/clk/qcom/dispcc-sc7180.c +++ b/drivers/clk/qcom/dispcc-sc7180.c @@ -202,7 +202,6 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { .name = "disp_cc_mdss_dp_crypto_clk_src", .parent_data = disp_cc_parent_data_1, .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, }, }; @@ -216,7 +215,6 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { .name = "disp_cc_mdss_dp_link_clk_src", .parent_data = disp_cc_parent_data_1, .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, }, }; @@ -230,7 +228,6 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { .name = "disp_cc_mdss_dp_pixel_clk_src", .parent_data = disp_cc_parent_data_1, .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), - .flags = CLK_SET_RATE_PARENT, .ops = &clk_dp_ops, }, }; -- Sent by a computer, using git, on the internet