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[213.245.241.245]) by smtp.gmail.com with ESMTPSA id q186sm6818274wma.45.2020.09.03.13.30.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Sep 2020 13:30:43 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= To: Maxime Ripard , Chen-Yu Tsai , Rob Herring , Mark Brown , Liam Girdwood Cc: devicetree@vger.kernel.org, Jernej Skrabec , alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, Takashi Iwai , Marcus Cooper , linux-sunxi@googlegroups.com, linux-arm-kernel@lists.infradead.org, =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= Subject: [PATCH v2 01/20] Revert "ASoC: sun4i-i2s: Fix the LRCK polarity" Date: Thu, 3 Sep 2020 22:30:15 +0200 Message-Id: <20200903203034.1057334-2-peron.clem@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200903203034.1057334-1-peron.clem@gmail.com> References: <20200903203034.1057334-1-peron.clem@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This reverts commit dd657eae8164f7e4bafe8b875031a7c6c50646a9. There was a misinterpretation of the analysis using a scope. After rechecking this using a logical analyzer the LRCK polarity is fine. Fixes: dd657eae8164 ("ASoC: sun4i-i2s: Fix the LRCK polarity") Signed-off-by: Clément Péron --- sound/soc/sunxi/sun4i-i2s.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index f23ff29e7c1d..fabff7bcccbc 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -603,29 +603,23 @@ static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, u32 mode, val; u8 offset; - /* - * DAI clock polarity - * - * The setup for LRCK contradicts the datasheet, but under a - * scope it's clear that the LRCK polarity is reversed - * compared to the expected polarity on the bus. - */ + /* DAI clock polarity */ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { case SND_SOC_DAIFMT_IB_IF: /* Invert both clocks */ - val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED; + val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED | + SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED; break; case SND_SOC_DAIFMT_IB_NF: /* Invert bit clock */ - val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED | - SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED; + val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED; break; case SND_SOC_DAIFMT_NB_IF: /* Invert frame clock */ - val = 0; + val = SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED; break; case SND_SOC_DAIFMT_NB_NF: - val = SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED; + val = 0; break; default: return -EINVAL; -- 2.25.1