From: Borislav Petkov <bp@alien8.de>
To: Krish Sadhukhan <krish.sadhukhan@oracle.com>
Cc: kvm@vger.kernel.org, pbonzini@redhat.com, jmattson@google.com,
tglx@linutronix.de, mingo@redhat.com, x86@kernel.org,
sean.j.christopherson@intel.com, vkuznets@redhat.com,
wanpengli@tencent.com, joro@8bytes.org,
dave.hansen@linux.intel.com, luto@kernel.org,
peterz@infradead.org, linux-kernel@vger.kernel.org,
hpa@zytor.com, Tom Lendacky <thomas.lendacky@amd.com>
Subject: Re: [PATCH 2/4 v3] x86: AMD: Add hardware-enforced cache coherency as a CPUID feature
Date: Fri, 11 Sep 2020 23:33:56 +0200 [thread overview]
Message-ID: <20200911213356.GC4110@zn.tnic> (raw)
In-Reply-To: <20200911192601.9591-3-krish.sadhukhan@oracle.com>
+ Tom.
On Fri, Sep 11, 2020 at 07:25:59PM +0000, Krish Sadhukhan wrote:
> +#define X86_FEATURE_HW_CACHE_COHERENCY (11*32+ 7) /* AMD hardware-enforced cache coherency */
so before you guys paint the bikeshed all kinds of colors :), Tom (CCed)
is digging out the official name. (If it is even uglier, we might keep
on bikeshedding...).
Once you have that, add the "" after the comment - like
X86_FEATURE_FENCE_SWAPGS_USER, for example, so that it doesn't show in
/proc/cpuinfo as luserspace doesn't care about hw coherency between enc
memory.
Thx.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
next prev parent reply other threads:[~2020-09-11 21:34 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-11 19:25 [PATCH 0/4 v3] x86: AMD: Don't flush cache if hardware enforces cache coherency across encryption domains Krish Sadhukhan
2020-09-11 19:25 ` [PATCH 1/4 v3] x86: AMD: Replace numeric value for SME CPUID leaf with a #define Krish Sadhukhan
2020-09-11 21:21 ` Borislav Petkov
2020-09-12 6:54 ` Paolo Bonzini
2020-09-11 19:25 ` [PATCH 2/4 v3] x86: AMD: Add hardware-enforced cache coherency as a CPUID feature Krish Sadhukhan
2020-09-11 19:36 ` Dave Hansen
2020-09-11 20:10 ` Krish Sadhukhan
2020-09-11 20:58 ` Dave Hansen
2020-09-11 21:33 ` Borislav Petkov [this message]
2020-09-11 21:44 ` Tom Lendacky
2020-09-11 19:26 ` [PATCH 3/4 v3] x86: AMD: Don't flush cache if hardware enforces cache coherency across encryption domnains Krish Sadhukhan
2020-09-11 19:26 ` [PATCH 4/4 v3] KVM: SVM: Don't flush cache if hardware enforces cache coherency across encryption domains Krish Sadhukhan
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