From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BFA3C43461 for ; Wed, 16 Sep 2020 16:51:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D17F5224D4 for ; Wed, 16 Sep 2020 16:51:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1600275109; bh=IpFNcwpgMGhaIjjYrhn3RrCKJAOKHJ/C9PHWEAEGuwc=; h=Date:From:To:Cc:Subject:References:In-Reply-To:List-ID:From; b=HEsTEPV/YY52xJcc0Lj/pgPLYievXjj1+FrJaHrI1YSNikT4wmh5a+wKYD/cTpGfQ 4Cn1WI/KKljLOEGpynO7W2aERAs/BYOOg62B3fgIvfQWTnjuKGNDpffNaWXgoo2jb5 jpNMFDCErAy4ogpmZwbCedCKbB799gZm5dcgfdg8= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726545AbgIPQvi (ORCPT ); Wed, 16 Sep 2020 12:51:38 -0400 Received: from mail.kernel.org ([198.145.29.99]:45318 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726382AbgIPQd2 (ORCPT ); Wed, 16 Sep 2020 12:33:28 -0400 Received: from localhost (unknown [122.172.186.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id A865A20658; Wed, 16 Sep 2020 12:46:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1600260402; bh=IpFNcwpgMGhaIjjYrhn3RrCKJAOKHJ/C9PHWEAEGuwc=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=wdmTyPZ+ChCahHH7J8zYPseh58htz4QL4nWTppk8PToYfyp1NH1p4VgPbS3HXQa51 ilxcZ4QKeNPFvJKXJ1P8b/qCjfgok7LdgE2zyYdvQ4vTGeiJKhSTpMx5m2x8hb+P4O KE6kvVoBMHD7zGdaj71NJNQyeLNWhzaYNBUqIYC0= Date: Wed, 16 Sep 2020 18:16:34 +0530 From: Vinod Koul To: Srinivas Kandagatla Cc: yung-chuan.liao@linux.intel.com, pierre-louis.bossart@linux.intel.com, sanyog.r.kale@intel.com, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 1/3] soundwire: qcom: clear BIT FIELDs before value set. Message-ID: <20200916124634.GM2968@vkoul-mobl> References: <20200916092125.30898-1-srinivas.kandagatla@linaro.org> <20200916092125.30898-2-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200916092125.30898-2-srinivas.kandagatla@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Srini, On 16-09-20, 10:21, Srinivas Kandagatla wrote: > According to usage (bitfields.h) of REG_FIELDS, > Modify is: > reg &= ~REG_FIELD_C; > reg |= FIELD_PREP(REG_FIELD_C, c); > > Patch ("soundwire: qcom : use FIELD_{GET|PREP}") seems to have > accidentally removed clearing bit field while modifying the register. > > Fix this by adding back clear register mask before setting it up! > > Signed-off-by: Srinivas Kandagatla > --- > drivers/soundwire/qcom.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c > index d7aabdaffee3..5d26361ab4f6 100644 > --- a/drivers/soundwire/qcom.c > +++ b/drivers/soundwire/qcom.c > @@ -311,6 +311,7 @@ static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl) > > /* Configure No pings */ > ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val); > + val &= ~SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK; > val |= FIELD_PREP(SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK, SWRM_DEF_CMD_NO_PINGS); Should we rather use u32_replace_bits() here, I think the intention is to replace bits. > ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val); > > @@ -372,6 +373,9 @@ static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus) > > ctrl->reg_read(ctrl, reg, &val); > > + val &= ~SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK; > + val &= ~SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK; > + > val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, SWRM_MAX_COL_VAL); > val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, SWRM_MAX_ROW_VAL); > > -- > 2.21.0 -- ~Vinod