From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
To: Florian Fainelli <florian@openwrt.org>,
linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] MIPS: SNI: Fix MIPS_L1_CACHE_SHIFT
Date: Thu, 17 Sep 2020 11:41:26 +0200 [thread overview]
Message-ID: <20200917094126.GA8484@alpha.franken.de> (raw)
In-Reply-To: <20200914160500.21356-1-tsbogend@alpha.franken.de>
On Mon, Sep 14, 2020 at 06:05:00PM +0200, Thomas Bogendoerfer wrote:
> Commit 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>") forgot
> to select the correct MIPS_L1_CACHE_SHIFT for SNI RM. This breaks non
> coherent DMA because of a wrong allocation alignment.
>
> Fixes: 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>")
> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> ---
> arch/mips/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
applied to mips-fixes.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
prev parent reply other threads:[~2020-09-17 9:59 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-14 16:05 [PATCH] MIPS: SNI: Fix MIPS_L1_CACHE_SHIFT Thomas Bogendoerfer
2020-09-17 9:41 ` Thomas Bogendoerfer [this message]
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