* [PATCH] MIPS: SNI: Fix MIPS_L1_CACHE_SHIFT
@ 2020-09-14 16:05 Thomas Bogendoerfer
2020-09-17 9:41 ` Thomas Bogendoerfer
0 siblings, 1 reply; 2+ messages in thread
From: Thomas Bogendoerfer @ 2020-09-14 16:05 UTC (permalink / raw)
To: Florian Fainelli, linux-mips, linux-kernel
Commit 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>") forgot
to select the correct MIPS_L1_CACHE_SHIFT for SNI RM. This breaks non
coherent DMA because of a wrong allocation alignment.
Fixes: 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>")
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
arch/mips/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index c95fa3a2484c..8f328298f8cc 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -877,6 +877,7 @@ config SNI_RM
select I8253
select I8259
select ISA
+ select MIPS_L1_CACHE_SHIFT_6
select SWAP_IO_SPACE if CPU_BIG_ENDIAN
select SYS_HAS_CPU_R4X00
select SYS_HAS_CPU_R5000
--
2.16.4
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH] MIPS: SNI: Fix MIPS_L1_CACHE_SHIFT
2020-09-14 16:05 [PATCH] MIPS: SNI: Fix MIPS_L1_CACHE_SHIFT Thomas Bogendoerfer
@ 2020-09-17 9:41 ` Thomas Bogendoerfer
0 siblings, 0 replies; 2+ messages in thread
From: Thomas Bogendoerfer @ 2020-09-17 9:41 UTC (permalink / raw)
To: Florian Fainelli, linux-mips, linux-kernel
On Mon, Sep 14, 2020 at 06:05:00PM +0200, Thomas Bogendoerfer wrote:
> Commit 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>") forgot
> to select the correct MIPS_L1_CACHE_SHIFT for SNI RM. This breaks non
> coherent DMA because of a wrong allocation alignment.
>
> Fixes: 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>")
> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> ---
> arch/mips/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
applied to mips-fixes.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
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