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[216.228.112.22]) by smtp.gmail.com with ESMTPSA id y202sm21433183pfc.179.2020.09.17.04.22.58 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 17 Sep 2020 04:22:58 -0700 (PDT) Date: Thu, 17 Sep 2020 04:19:41 -0700 From: Nicolin Chen To: Krzysztof Kozlowski Cc: Thierry Reding , Joerg Roedel , linux-tegra@vger.kernel.org, "linux-kernel@vger.kernel.org" , jonathanh@nvidia.com Subject: Re: [PATCH] memory: tegra: Correct num_tlb_lines for tegra210 Message-ID: <20200917111940.GA12912@Asurada-Nvidia> References: <20200915232803.26163-1-nicoleotsuka@gmail.com> <20200917104315.GI3515672@ulmo> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Sep 17, 2020 at 12:54:42PM +0200, Krzysztof Kozlowski wrote: > On Thu, 17 Sep 2020 at 12:43, Thierry Reding wrote: > > > > On Tue, Sep 15, 2020 at 04:28:03PM -0700, Nicolin Chen wrote: > > > According to Tegra210 TRM, the default value of TLB_ACTIVE_LINES > > > field of register MC_SMMU_TLB_CONFIG_0 is 0x30. So num_tlb_lines > > > should be 48 (0x30) rather than 32 (0x20). > > > > > > Signed-off-by: Nicolin Chen > > > --- > > > drivers/memory/tegra/tegra210.c | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > Please send this as part of a series including: > > > > https://patchwork.ozlabs.org/project/linux-tegra/patch/20200916002359.10823-1-nicoleotsuka@gmail.com/ > > > > Adding Joerg for visibility. From the Tegra side: > > > > Acked-by: Thierry Reding > > So basically applying this one alone breaks existing platforms and > makes history non-bisectable... > > Nicolin, the bisectability is important requirement so you must always > mention the dependencies between patches. Sorry. Will be careful next time. And I am resending both in a series. Thanks Nic