From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED8C3C43464 for ; Fri, 18 Sep 2020 03:08:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A0CE0206DB for ; Fri, 18 Sep 2020 03:08:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1600398494; bh=RQR8VA1lndg1uehp5I/ycFWXH/+9/WdrVm0E3mtajoE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=M93F/Mni97bB0TGVYulTGc5nx7lfZ6JYmtI0yz2rT6c/vi3DhjWgZ/AIEDROX1pOF 86cp71GibNRpyBppkONDdTShHM+PsaWAI1C5E+4G9tfcpYWVHF64I5TYIRlOmIc9pj DpBx/3iXdkQATkhX2D/iuNT3b1iekEp6sTx2X8GI= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730668AbgIRDIN (ORCPT ); Thu, 17 Sep 2020 23:08:13 -0400 Received: from mail.kernel.org ([198.145.29.99]:49976 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726314AbgIRCDe (ORCPT ); Thu, 17 Sep 2020 22:03:34 -0400 Received: from sasha-vm.mshome.net (c-73-47-72-35.hsd1.nh.comcast.net [73.47.72.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id C7AE4235F7; Fri, 18 Sep 2020 02:03:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1600394613; bh=RQR8VA1lndg1uehp5I/ycFWXH/+9/WdrVm0E3mtajoE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=C5m97RuJS7iiibzhqtUXYFRyigZJ71zYD615sxs0dNdJzD7Dlmg8OjRc/eWUddKS0 5Gnb4UuLRYI+vYXAk9xLaSlzVDTqunCyn6TTmhz2z3hxLcS/f1gSjIe4wf1VAItcBn 9d2aWfC/4nfSHbU+C+F7jWmL0BRGxiNFc7CS9IBQ= From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Mohan Kumar , Viswanath L , Takashi Iwai , Sasha Levin , alsa-devel@alsa-project.org Subject: [PATCH AUTOSEL 5.4 116/330] ALSA: hda: Clear RIRB status before reading WP Date: Thu, 17 Sep 2020 21:57:36 -0400 Message-Id: <20200918020110.2063155-116-sashal@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200918020110.2063155-1-sashal@kernel.org> References: <20200918020110.2063155-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mohan Kumar [ Upstream commit 6d011d5057ff88ee556c000ac6fe0be23bdfcd72 ] RIRB interrupt status getting cleared after the write pointer is read causes a race condition, where last response(s) into RIRB may remain unserviced by IRQ, eventually causing azx_rirb_get_response to fall back to polling mode. Clearing the RIRB interrupt status ahead of write pointer access ensures that this condition is avoided. Signed-off-by: Mohan Kumar Signed-off-by: Viswanath L Link: https://lore.kernel.org/r/1580983853-351-1-git-send-email-viswanathl@nvidia.com Signed-off-by: Takashi Iwai Signed-off-by: Sasha Levin --- sound/pci/hda/hda_controller.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/sound/pci/hda/hda_controller.c b/sound/pci/hda/hda_controller.c index 76b507058cb4d..5e6081750bd9b 100644 --- a/sound/pci/hda/hda_controller.c +++ b/sound/pci/hda/hda_controller.c @@ -1159,16 +1159,23 @@ irqreturn_t azx_interrupt(int irq, void *dev_id) if (snd_hdac_bus_handle_stream_irq(bus, status, stream_update)) active = true; - /* clear rirb int */ status = azx_readb(chip, RIRBSTS); if (status & RIRB_INT_MASK) { + /* + * Clearing the interrupt status here ensures that no + * interrupt gets masked after the RIRB wp is read in + * snd_hdac_bus_update_rirb. This avoids a possible + * race condition where codec response in RIRB may + * remain unserviced by IRQ, eventually falling back + * to polling mode in azx_rirb_get_response. + */ + azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); active = true; if (status & RIRB_INT_RESPONSE) { if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) udelay(80); snd_hdac_bus_update_rirb(bus); } - azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); } } while (active && ++repeat < 10); -- 2.25.1