From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59F96C43463 for ; Sun, 20 Sep 2020 14:18:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 228DF235F9 for ; Sun, 20 Sep 2020 14:18:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726550AbgITOSO (ORCPT ); Sun, 20 Sep 2020 10:18:14 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:46010 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726305AbgITOSN (ORCPT ); Sun, 20 Sep 2020 10:18:13 -0400 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1kK0AH-00FTwj-Sv; Sun, 20 Sep 2020 16:18:05 +0200 Date: Sun, 20 Sep 2020 16:18:05 +0200 From: Andrew Lunn To: Robert Marko Cc: hkallweit1@gmail.com, linux@armlinux.org.uk, davem@davemloft.net, kuba@kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Luka Perkov Subject: Re: [PATCH v4 2/2] net: mdio-ipq4019: add Clause 45 support Message-ID: <20200920141805.GA3689762@lunn.ch> References: <20200920141653.357493-1-robert.marko@sartura.hr> <20200920141653.357493-3-robert.marko@sartura.hr> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200920141653.357493-3-robert.marko@sartura.hr> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, Sep 20, 2020 at 04:16:53PM +0200, Robert Marko wrote: > While up-streaming the IPQ4019 driver it was thought that the controller had no Clause 45 support, > but it actually does and its activated by writing a bit to the mode register. > > So lets add it as newer SoC-s use the same controller and Clause 45 compliant PHY-s. > > Signed-off-by: Robert Marko > Cc: Luka Perkov Reviewed-by: Andrew Lunn Andrew