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Peter Anvin" , Jiri Olsa , Mark Rutland , Michael Petlan , Namhyung Kim , Stephane Eranian , x86@kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/4] perf/amd/uncore: Allow F19h user coreid, threadmask, and sliceid specification Date: Mon, 21 Sep 2020 09:43:29 -0500 Message-Id: <20200921144330.6331-4-kim.phillips@amd.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200921144330.6331-1-kim.phillips@amd.com> References: <20200921144330.6331-1-kim.phillips@amd.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SN4PR0401CA0040.namprd04.prod.outlook.com (2603:10b6:803:2a::26) To BN8PR12MB2946.namprd12.prod.outlook.com (2603:10b6:408:9d::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from fritz.amd.com (165.204.77.11) by SN4PR0401CA0040.namprd04.prod.outlook.com (2603:10b6:803:2a::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3391.15 via Frontend Transport; Mon, 21 Sep 2020 14:44:21 +0000 X-Mailer: git-send-email 2.27.0 X-Originating-IP: [165.204.77.11] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 0052757b-316c-4bf6-4bc6-08d85e3cd4f2 X-MS-TrafficTypeDiagnostic: BN6PR12MB1459: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ZspdDkbWLIg+ky8vpbVkItxAKoiN9O6AXiTf+lY8LcjldbQ/VcmVszF1RNv37xfAi4E5vihwufox6afFiydvy6fKnhl6kdU00CiorKVjEQ0lg09JE9yikXIabxGIv3TAFF372e6b+o8nSmFeVvrswnpO7Ll+WFjxVLgWvxfgjZRvpE77CFdU299bcpj/fGG1YYnPEa5ApTykeLlZWcTzvcMadkBarc1QJidgd5ydMEFd23EZAkbLK2hEKH/TxdOjGdTagwhVxzb99FkzxYoXSv6KT5OhW50qXhZu/Ss+1IWefMdufWY0WAjQiqkdmCOD7nOTtb/ELRmpRcm/cqQV1jRY/5Qnmptd78g1sBaDogjYnx80ix5VfKU6dDFxVUUK X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:BN8PR12MB2946.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(4636009)(346002)(39860400002)(376002)(366004)(396003)(136003)(66556008)(956004)(2616005)(8936002)(7049001)(44832011)(8676002)(4326008)(6486002)(110136005)(83380400001)(54906003)(186003)(16526019)(7696005)(52116002)(26005)(86362001)(478600001)(2906002)(316002)(36756003)(5660300002)(7416002)(1076003)(66476007)(66946007);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData: zqGaKOUSsAhGb2emLg9+31mUm+rELwxGepUrMI4VmdrocgXOPhbq1wgLi1iNyVKVk9ocuRRk18YpwIN9SIzvHeTryF83nk1zIhvFDh1+ge0gJxm/NvzLPuZiDRzSPzqEeVY7bO7wiPswim76E6vr1pvkGomA76d/9oJdyIXRUd95scJMBrlzvLYKe6bcWrGScDvuzNqLVu70FgESOI2DNqX/WEvEBce9F111Ui1nnktbBJ0c+8QZWk35Jb2NuV2ST/nqKVxIDwDmhFanlXwPP30eQ2miGiPTGCkM5/VilZ0l13DAEmWZcVVnFLv++vV5IftatA2T0qotfsNCMrJvzxohwE6dki875XUf2/8bA3g6q2J13wEL4O6cMRAFqcYeHdS4vab8HHvD1cDGsLAC97TGu6nDY9T7IjugxiktOMWeLfbRfSg+IFlf48CKWvcIozuAx/6ct/MgS8e5hBWB0sGbyAbj4uYPyYiJyYYG9UCXMcQeuYUVDEP99wZBXt6e9ZSmIZcyY1wXXCvvizaFPz7WDB+5wJqGvSYPzAqBgNnA+AsUPbn3voRferNXzKU6o4y5vbAsMb98ozfCfJ0zJD/NMlzkqjLpUJpiyuh0Hyy+o9R1yl5m7P42USEbcld6y53y+UH53e664VbFbwfYjg== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0052757b-316c-4bf6-4bc6-08d85e3cd4f2 X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB2946.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Sep 2020 14:44:23.8541 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: T9OCT9hd0WCOVVIAE6xopY2wkScnJKwCpI1NIRA5qsqkwqcZUc8DKuOznYA1sbG/VokR7ZQTp3fROzdTvTssSw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1459 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Family 19h, the driver checks for a populated 2-bit threadmask in order to establish that the user wants to measure individual slices, individual cores (only one can be measured at a time), and lets the user also directly specify enallcores and/or enallslices if desired. Example F19h invocation to measure L3 accesses (event 4, umask 0xff) by the first thread (id 0 -> mask 0x1) of the first core (id 0) on the first slice (id 0): perf stat -a -e instructions,amd_l3/umask=0xff,event=0x4,coreid=0,threadmask=1,sliceid=0,enallcores=0,enallslices=0/ Signed-off-by: Kim Phillips Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: Borislav Petkov Cc: "H. Peter Anvin" Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Michael Petlan Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Thomas Gleixner Cc: x86@kernel.org Cc: linux-kernel@vger.kernel.org --- arch/x86/events/amd/uncore.c | 37 +++++++++++++++++++++++++++++++----- 1 file changed, 32 insertions(+), 5 deletions(-) diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c index 1e35c934fe7c..f026715a39d2 100644 --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -190,8 +190,19 @@ static u64 l3_thread_slice_mask(u64 config) return ((config & AMD64_L3_SLICE_MASK) ? : AMD64_L3_SLICE_MASK) | ((config & AMD64_L3_THREAD_MASK) ? : AMD64_L3_THREAD_MASK); - return AMD64_L3_EN_ALL_SLICES | AMD64_L3_EN_ALL_CORES | - AMD64_L3_F19H_THREAD_MASK; + /* + * If the user doesn't specify a threadmask, they're not trying to + * count core 0, so we enable all cores & threads. + * We'll also assume that they want to count slice 0 if they specify + * a threadmask and leave sliceid and enallslices unpopulated. + */ + if (!(config & AMD64_L3_F19H_THREAD_MASK)) + return AMD64_L3_F19H_THREAD_MASK | AMD64_L3_EN_ALL_SLICES | + AMD64_L3_EN_ALL_CORES; + + return config & (AMD64_L3_F19H_THREAD_MASK | AMD64_L3_SLICEID_MASK | + AMD64_L3_EN_ALL_CORES | AMD64_L3_EN_ALL_SLICES | + AMD64_L3_COREID_MASK); } static int amd_uncore_event_init(struct perf_event *event) @@ -278,8 +289,13 @@ DEFINE_UNCORE_FORMAT_ATTR(event12, event, "config:0-7,32-35"); DEFINE_UNCORE_FORMAT_ATTR(event14, event, "config:0-7,32-35,59-60"); /* F17h+ DF */ DEFINE_UNCORE_FORMAT_ATTR(event8, event, "config:0-7"); /* F17h+ L3 */ DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15"); +DEFINE_UNCORE_FORMAT_ATTR(coreid, coreid, "config:42-44"); /* F19h L3 */ DEFINE_UNCORE_FORMAT_ATTR(slicemask, slicemask, "config:48-51"); /* F17h L3 */ DEFINE_UNCORE_FORMAT_ATTR(threadmask8, threadmask, "config:56-63"); /* F17h L3 */ +DEFINE_UNCORE_FORMAT_ATTR(threadmask2, threadmask, "config:56-57"); /* F19h L3 */ +DEFINE_UNCORE_FORMAT_ATTR(enallslices, enallslices, "config:46"); /* F19h L3 */ +DEFINE_UNCORE_FORMAT_ATTR(enallcores, enallcores, "config:47"); /* F19h L3 */ +DEFINE_UNCORE_FORMAT_ATTR(sliceid, sliceid, "config:48-50"); /* F19h L3 */ static struct attribute *amd_uncore_df_format_attr[] = { &format_attr_event12.attr, /* event14 if F17h+ */ @@ -290,8 +306,11 @@ static struct attribute *amd_uncore_df_format_attr[] = { static struct attribute *amd_uncore_l3_format_attr[] = { &format_attr_event12.attr, /* event8 if F17h+ */ &format_attr_umask.attr, - NULL, /* slicemask if F17h */ - NULL, /* threadmask8 if F17h */ + NULL, /* slicemask if F17h, coreid if F19h */ + NULL, /* threadmask8 if F17h, enallslices if F19h */ + NULL, /* enallcores if F19h */ + NULL, /* sliceid if F19h */ + NULL, /* threadmask2 if F19h */ NULL, }; @@ -583,7 +602,15 @@ static int __init amd_uncore_init(void) } if (boot_cpu_has(X86_FEATURE_PERFCTR_LLC)) { - if (boot_cpu_data.x86 >= 0x17) { + if (boot_cpu_data.x86 >= 0x19) { + *l3_attr++ = &format_attr_event8.attr; + *l3_attr++ = &format_attr_umask.attr; + *l3_attr++ = &format_attr_coreid.attr; + *l3_attr++ = &format_attr_enallslices.attr; + *l3_attr++ = &format_attr_enallcores.attr; + *l3_attr++ = &format_attr_sliceid.attr; + *l3_attr++ = &format_attr_threadmask2.attr; + } else if (boot_cpu_data.x86 >= 0x17) { *l3_attr++ = &format_attr_event8.attr; *l3_attr++ = &format_attr_umask.attr; *l3_attr++ = &format_attr_slicemask.attr; -- 2.27.0