* [net] net: mscc: ocelot: fix fields offset in SG_CONFIG_REG_3
@ 2020-09-24 2:11 Xiaoliang Yang
2020-09-24 7:08 ` Alexandre Belloni
2020-09-25 3:02 ` David Miller
0 siblings, 2 replies; 4+ messages in thread
From: Xiaoliang Yang @ 2020-09-24 2:11 UTC (permalink / raw)
To: xiaoliang.yang_1, davem, netdev, linux-kernel, allan.nielsen,
joergen.andreasen, UNGLinuxDriver, alexandre.belloni, fido_max,
alexandru.marginean, po.liu, claudiu.manoil, vladimir.oltean,
leoyang.li
INIT_IPS and GATE_ENABLE fields have a wrong offset in SG_CONFIG_REG_3.
This register is used by stream gate control of PSFP, and it has not
been used before, because PSFP is not implemented in ocelot driver.
Signed-off-by: Xiaoliang Yang <xiaoliang.yang_1@nxp.com>
---
include/soc/mscc/ocelot_ana.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/soc/mscc/ocelot_ana.h b/include/soc/mscc/ocelot_ana.h
index 841c6ec22b64..1669481d9779 100644
--- a/include/soc/mscc/ocelot_ana.h
+++ b/include/soc/mscc/ocelot_ana.h
@@ -252,10 +252,10 @@
#define ANA_SG_CONFIG_REG_3_LIST_LENGTH_M GENMASK(18, 16)
#define ANA_SG_CONFIG_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(18, 16)) >> 16)
#define ANA_SG_CONFIG_REG_3_GATE_ENABLE BIT(20)
-#define ANA_SG_CONFIG_REG_3_INIT_IPS(x) (((x) << 24) & GENMASK(27, 24))
-#define ANA_SG_CONFIG_REG_3_INIT_IPS_M GENMASK(27, 24)
-#define ANA_SG_CONFIG_REG_3_INIT_IPS_X(x) (((x) & GENMASK(27, 24)) >> 24)
-#define ANA_SG_CONFIG_REG_3_INIT_GATE_STATE BIT(28)
+#define ANA_SG_CONFIG_REG_3_INIT_IPS(x) (((x) << 21) & GENMASK(24, 21))
+#define ANA_SG_CONFIG_REG_3_INIT_IPS_M GENMASK(24, 21)
+#define ANA_SG_CONFIG_REG_3_INIT_IPS_X(x) (((x) & GENMASK(24, 21)) >> 21)
+#define ANA_SG_CONFIG_REG_3_INIT_GATE_STATE BIT(25)
#define ANA_SG_GCL_GS_CONFIG_RSZ 0x4
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [net] net: mscc: ocelot: fix fields offset in SG_CONFIG_REG_3
2020-09-24 2:11 [net] net: mscc: ocelot: fix fields offset in SG_CONFIG_REG_3 Xiaoliang Yang
@ 2020-09-24 7:08 ` Alexandre Belloni
2020-09-24 8:49 ` [EXT] " Xiaoliang Yang
2020-09-25 3:02 ` David Miller
1 sibling, 1 reply; 4+ messages in thread
From: Alexandre Belloni @ 2020-09-24 7:08 UTC (permalink / raw)
To: Xiaoliang Yang
Cc: davem, netdev, linux-kernel, allan.nielsen, joergen.andreasen,
UNGLinuxDriver, fido_max, alexandru.marginean, po.liu,
claudiu.manoil, vladimir.oltean, leoyang.li
Hi,
On 24/09/2020 10:11:13+0800, Xiaoliang Yang wrote:
> INIT_IPS and GATE_ENABLE fields have a wrong offset in SG_CONFIG_REG_3.
You are changing GATE_STATE, not GATE_ENABLE
> This register is used by stream gate control of PSFP, and it has not
> been used before, because PSFP is not implemented in ocelot driver.
>
> Signed-off-by: Xiaoliang Yang <xiaoliang.yang_1@nxp.com>
> ---
> include/soc/mscc/ocelot_ana.h | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/include/soc/mscc/ocelot_ana.h b/include/soc/mscc/ocelot_ana.h
> index 841c6ec22b64..1669481d9779 100644
> --- a/include/soc/mscc/ocelot_ana.h
> +++ b/include/soc/mscc/ocelot_ana.h
> @@ -252,10 +252,10 @@
> #define ANA_SG_CONFIG_REG_3_LIST_LENGTH_M GENMASK(18, 16)
> #define ANA_SG_CONFIG_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(18, 16)) >> 16)
> #define ANA_SG_CONFIG_REG_3_GATE_ENABLE BIT(20)
> -#define ANA_SG_CONFIG_REG_3_INIT_IPS(x) (((x) << 24) & GENMASK(27, 24))
> -#define ANA_SG_CONFIG_REG_3_INIT_IPS_M GENMASK(27, 24)
> -#define ANA_SG_CONFIG_REG_3_INIT_IPS_X(x) (((x) & GENMASK(27, 24)) >> 24)
> -#define ANA_SG_CONFIG_REG_3_INIT_GATE_STATE BIT(28)
> +#define ANA_SG_CONFIG_REG_3_INIT_IPS(x) (((x) << 21) & GENMASK(24, 21))
> +#define ANA_SG_CONFIG_REG_3_INIT_IPS_M GENMASK(24, 21)
> +#define ANA_SG_CONFIG_REG_3_INIT_IPS_X(x) (((x) & GENMASK(24, 21)) >> 21)
> +#define ANA_SG_CONFIG_REG_3_INIT_GATE_STATE BIT(25)
>
VSC7514 doesn't have the stream gate registers ans this was generated
automatically from the cml file for felix. Did that change?
Seeing that bits in this register are not packed, I would believe your
change is correct.
> #define ANA_SG_GCL_GS_CONFIG_RSZ 0x4
>
> --
> 2.17.1
>
--
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: [EXT] Re: [net] net: mscc: ocelot: fix fields offset in SG_CONFIG_REG_3
2020-09-24 7:08 ` Alexandre Belloni
@ 2020-09-24 8:49 ` Xiaoliang Yang
0 siblings, 0 replies; 4+ messages in thread
From: Xiaoliang Yang @ 2020-09-24 8:49 UTC (permalink / raw)
To: Alexandre Belloni
Cc: davem@davemloft.net, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org, allan.nielsen@microchip.com,
joergen.andreasen@microchip.com, UNGLinuxDriver@microchip.com,
fido_max@inbox.ru, Alexandru Marginean, Po Liu, Claudiu Manoil,
Vladimir Oltean, Leo Li
Hi Alexandre,
On 24/09/2020 15:08:21+0800, Alexandre Belloni wrote:
>
> Hi,
>
> On 24/09/2020 10:11:13+0800, Xiaoliang Yang wrote:
> > INIT_IPS and GATE_ENABLE fields have a wrong offset in SG_CONFIG_REG_3.
>
> You are changing GATE_STATE, not GATE_ENABLE
Oh, sorry, it should be GATE_STATE field.
>
> > This register is used by stream gate control of PSFP, and it has not
> > been used before, because PSFP is not implemented in ocelot driver.
> >
> > Signed-off-by: Xiaoliang Yang <xiaoliang.yang_1@nxp.com>
> > ---
> > include/soc/mscc/ocelot_ana.h | 8 ++++----
> > 1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/include/soc/mscc/ocelot_ana.h
> > b/include/soc/mscc/ocelot_ana.h index 841c6ec22b64..1669481d9779
> > 100644
> > --- a/include/soc/mscc/ocelot_ana.h
> > +++ b/include/soc/mscc/ocelot_ana.h
> > @@ -252,10 +252,10 @@
> > #define ANA_SG_CONFIG_REG_3_LIST_LENGTH_M
> GENMASK(18, 16)
> > #define ANA_SG_CONFIG_REG_3_LIST_LENGTH_X(x) (((x)
> & GENMASK(18, 16)) >> 16)
> > #define ANA_SG_CONFIG_REG_3_GATE_ENABLE
> BIT(20)
> > -#define ANA_SG_CONFIG_REG_3_INIT_IPS(x) (((x) <<
> 24) & GENMASK(27, 24))
> > -#define ANA_SG_CONFIG_REG_3_INIT_IPS_M
> GENMASK(27, 24)
> > -#define ANA_SG_CONFIG_REG_3_INIT_IPS_X(x) (((x) &
> GENMASK(27, 24)) >> 24)
> > -#define ANA_SG_CONFIG_REG_3_INIT_GATE_STATE
> BIT(28)
> > +#define ANA_SG_CONFIG_REG_3_INIT_IPS(x) (((x) <<
> 21) & GENMASK(24, 21))
> > +#define ANA_SG_CONFIG_REG_3_INIT_IPS_M
> GENMASK(24, 21)
> > +#define ANA_SG_CONFIG_REG_3_INIT_IPS_X(x) (((x) &
> GENMASK(24, 21)) >> 21)
> > +#define ANA_SG_CONFIG_REG_3_INIT_GATE_STATE
> BIT(25)
> >
>
> VSC7514 doesn't have the stream gate registers ans this was generated
> automatically from the cml file for felix. Did that change?
>
> Seeing that bits in this register are not packed, I would believe your change is
> correct.
Yes, this register is in VSC9959, we need it in PSFP gate control function for felix in future. I have tested on VSC9959, the bit offsets are not correct.
Thanks,
Xiaoliang Yang
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [net] net: mscc: ocelot: fix fields offset in SG_CONFIG_REG_3
2020-09-24 2:11 [net] net: mscc: ocelot: fix fields offset in SG_CONFIG_REG_3 Xiaoliang Yang
2020-09-24 7:08 ` Alexandre Belloni
@ 2020-09-25 3:02 ` David Miller
1 sibling, 0 replies; 4+ messages in thread
From: David Miller @ 2020-09-25 3:02 UTC (permalink / raw)
To: xiaoliang.yang_1
Cc: netdev, linux-kernel, allan.nielsen, joergen.andreasen,
UNGLinuxDriver, alexandre.belloni, fido_max, alexandru.marginean,
po.liu, claudiu.manoil, vladimir.oltean, leoyang.li
From: Xiaoliang Yang <xiaoliang.yang_1@nxp.com>
Date: Thu, 24 Sep 2020 10:11:13 +0800
> INIT_IPS and GATE_ENABLE fields have a wrong offset in SG_CONFIG_REG_3.
> This register is used by stream gate control of PSFP, and it has not
> been used before, because PSFP is not implemented in ocelot driver.
>
> Signed-off-by: Xiaoliang Yang <xiaoliang.yang_1@nxp.com>
Applied and queued up for -stable.
^ permalink raw reply [flat|nested] 4+ messages in thread
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2020-09-24 2:11 [net] net: mscc: ocelot: fix fields offset in SG_CONFIG_REG_3 Xiaoliang Yang
2020-09-24 7:08 ` Alexandre Belloni
2020-09-24 8:49 ` [EXT] " Xiaoliang Yang
2020-09-25 3:02 ` David Miller
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