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From: kholk11@gmail.com
To: robdclark@gmail.com
Cc: sean@poorly.run, airlied@linux.ie, daniel@ffwll.ch,
	jcrouse@codeaurora.org, konradybcio@gmail.com, kholk11@gmail.com,
	marijns95@gmail.com, martin.botka1@gmail.com,
	linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org,
	phone-devel@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v2 4/7] drm/msm/a5xx: Reset VBIF before PC only on A510 and A530
Date: Mon, 28 Sep 2020 22:47:06 +0200	[thread overview]
Message-ID: <20200928204709.45746-5-kholk11@gmail.com> (raw)
In-Reply-To: <20200928204709.45746-1-kholk11@gmail.com>

From: AngeloGioacchino Del Regno <kholk11@gmail.com>

Resetting the VBIF before power collapse is done to avoid getting
bogus FIFO entries during the suspend sequence or subsequent resume,
but this is doable only on Adreno 510 and Adreno 530, as the other
units will tendentially lock up.
Especially on Adreno 508, the GPU will show lockups and very bad
slownesses after processing the first frame.

Avoiding to execute the RBBM SW Reset before suspend will stop the
lockup issue from happening on at least Adreno 508/509/512.

Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>
---
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index fd33a34961cc..6163c3b61a69 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -1306,10 +1306,12 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu)
 
 	/*
 	 * Reset the VBIF before power collapse to avoid issue with FIFO
-	 * entries
+	 * entries on Adreno A510 and A530 (the others will tend to lock up)
 	 */
-	gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x003C0000);
-	gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x00000000);
+	if (adreno_is_a510(adreno_gpu) || adreno_is_a530(adreno_gpu)) {
+		gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x003C0000);
+		gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x00000000);
+	}
 
 	return msm_gpu_pm_suspend(gpu);
 }
-- 
2.28.0


  parent reply	other threads:[~2020-09-28 20:47 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-28 20:47 [PATCH v2 0/7] Add support for Adreno 508/509/512 kholk11
2020-09-28 20:47 ` [PATCH v2 1/7] drm/msm/a5xx: Remove overwriting A5XX_PC_DBG_ECO_CNTL register kholk11
2020-09-28 20:47 ` [PATCH v2 2/7] drm/msm/a5xx: Separate A5XX_PC_DBG_ECO_CNTL write from main branch kholk11
2020-09-28 20:47 ` [PATCH v2 3/7] drm/msm/a5xx: Add support for Adreno 508, 509, 512 GPUs kholk11
2020-11-01 18:58   ` Rob Clark
2020-09-28 20:47 ` kholk11 [this message]
2020-09-28 20:47 ` [PATCH v2 5/7] drm/msm/a5xx: Fix VPC protect value in gpu_write() kholk11
2020-09-28 20:47 ` [PATCH v2 6/7] drm/msm/a5xx: Disable flat shading optimization kholk11
2020-09-28 20:47 ` [PATCH v2 7/7] drm/msm/a5xx: Disable UCHE global filter kholk11

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