From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBAE8C43457 for ; Mon, 12 Oct 2020 18:04:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A1C562076D for ; Mon, 12 Oct 2020 18:04:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Dm0phudP" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404164AbgJLSEb (ORCPT ); Mon, 12 Oct 2020 14:04:31 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:38384 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2404133AbgJLSEZ (ORCPT ); Mon, 12 Oct 2020 14:04:25 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 09CI4GT9105224; Mon, 12 Oct 2020 13:04:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1602525856; bh=r84SiCjn9/W8+yMMq2kABKjatvatKw7U1heQ5CvxrDw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Dm0phudPO6FQnOqjbyJx63xszBFxQEilozMcVOmMUroNDKzhDmdnkS1rajqTWZjah ly9skhQzyiSDbZkIgVSBdzEkDyLhh+GDCGvvOAEbsYi+WCINFBleHWOi1+ibbDtXSB 4/CslMbkleMjFzDGC+tdNvzlbuXjcmC2qiYYyRIg= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 09CI4GPQ099553 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 12 Oct 2020 13:04:16 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 12 Oct 2020 13:04:15 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 12 Oct 2020 13:04:15 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 09CI45j5021531; Mon, 12 Oct 2020 13:04:13 -0500 From: Pratyush Yadav To: Tudor Ambarus , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , , CC: Pratyush Yadav Subject: [PATCH 3/3] mtd: spi-nor: core: Introduce SPI_NOR_NO_MULTI_PASS_PP Date: Mon, 12 Oct 2020 23:34:04 +0530 Message-ID: <20201012180404.6476-4-p.yadav@ti.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201012180404.6476-1-p.yadav@ti.com> References: <20201012180404.6476-1-p.yadav@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Cypress Semper S28 flash family uses 2-bit ECC by default. Under this ECC scheme, multi-pass page programs result in a program error. This means that unlike many other SPI NOR flashes, bit-walking cannot be done. In other words, once a page is programmed, its bits cannot then be flipped to 0 without an erase in between. This causes problems with UBIFS because it uses bit-walking to clear EC and VID magic numbers from a PEB before issuing an erase to preserve the file system correctness in case of power cuts. Use SPI_NOR_NO_MULTI_PASS_PP to set MTD_NO_MULTI_PASS_WRITE, telling upper layers to avoid multi-pass page programming. In addition, update mtd->writesize to match the page size to make sure upper layers make the changes they need in one single go. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 5 +++++ drivers/mtd/spi-nor/core.h | 6 ++++++ drivers/mtd/spi-nor/spansion.c | 2 +- 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index ff592468cc15..16d4bcfe7b10 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -3469,6 +3469,11 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, nor->page_size = nor->params->page_size; mtd->writebufsize = nor->page_size; + if (info->flags & SPI_NOR_NO_MULTI_PASS_PP) { + mtd->flags |= MTD_NO_MULTI_PASS_WRITE; + mtd->writesize = nor->page_size; + } + if (of_property_read_bool(np, "broken-flash-reset")) nor->flags |= SNOR_F_BROKEN_RESET; diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 0a775a7b5606..3394b7474c08 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -329,6 +329,12 @@ struct flash_info { * available I/O mode via a * volatile bit. */ +#define SPI_NOR_NO_MULTI_PASS_PP BIT(22) /* + * Once a page is programmed it + * cannot be programmed again + * without an erase operation in + * between. + */ /* Part specific fixup hooks. */ const struct spi_nor_fixups *fixups; diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 2c5c0f69dc5c..72430cd4e6af 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -275,7 +275,7 @@ static const struct flash_info spansion_parts[] = { SPI_NOR_NO_ERASE) }, { "s28hs512t", INFO(0x345b1a, 0, 256 * 1024, 256, SECT_4K | SPI_NOR_OCTAL_DTR_READ | - SPI_NOR_OCTAL_DTR_PP) + SPI_NOR_OCTAL_DTR_PP | SPI_NOR_NO_MULTI_PASS_PP) .fixups = &s28hs512t_fixups, }, }; -- 2.28.0