From: Marc Zyngier <maz@kernel.org>
To: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>,
Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Nagarjuna Kristam <nkristam@nvidia.com>,
Sowjanya Komatineni <skomatineni@nvidia.com>,
devicetree@vger.kernel.org
Subject: [PATCH] arm64: tegra186: Add missing CPU PMUs
Date: Tue, 13 Oct 2020 10:58:51 +0100 [thread overview]
Message-ID: <20201013095851.311478-1-maz@kernel.org> (raw)
Add the description of CPU PMUs for both the Denver and A57 clusters,
which enables the perf subsystem.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 28 +++++++++++++++++++-----
1 file changed, 22 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index fd44545e124d..6bb03668a8d3 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1321,7 +1321,7 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ denver_0: cpu@0 {
compatible = "nvidia,tegra186-denver";
device_type = "cpu";
i-cache-size = <0x20000>;
@@ -1334,7 +1334,7 @@ cpu@0 {
reg = <0x000>;
};
- cpu@1 {
+ denver_1: cpu@1 {
compatible = "nvidia,tegra186-denver";
device_type = "cpu";
i-cache-size = <0x20000>;
@@ -1347,7 +1347,7 @@ cpu@1 {
reg = <0x001>;
};
- cpu@2 {
+ ca57_0: cpu@2 {
compatible = "arm,cortex-a57";
device_type = "cpu";
i-cache-size = <0xC000>;
@@ -1360,7 +1360,7 @@ cpu@2 {
reg = <0x100>;
};
- cpu@3 {
+ ca57_1: cpu@3 {
compatible = "arm,cortex-a57";
device_type = "cpu";
i-cache-size = <0xC000>;
@@ -1373,7 +1373,7 @@ cpu@3 {
reg = <0x101>;
};
- cpu@4 {
+ ca57_2: cpu@4 {
compatible = "arm,cortex-a57";
device_type = "cpu";
i-cache-size = <0xC000>;
@@ -1386,7 +1386,7 @@ cpu@4 {
reg = <0x102>;
};
- cpu@5 {
+ ca57_3: cpu@5 {
compatible = "arm,cortex-a57";
device_type = "cpu";
i-cache-size = <0xC000>;
@@ -1418,6 +1418,22 @@ L2_A57: l2-cache1 {
};
};
+ pmu_denver {
+ compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3";
+ interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&denver_0 &denver_1>;
+ };
+
+ pmu_a57 {
+ compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
+ interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>;
+ };
+
thermal-zones {
a57 {
polling-delay = <0>;
--
2.28.0
next reply other threads:[~2020-10-13 9:59 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-13 9:58 Marc Zyngier [this message]
2020-11-10 17:36 ` [PATCH] arm64: tegra186: Add missing CPU PMUs Thierry Reding
2020-11-10 18:08 ` Marc Zyngier
2020-11-10 18:22 ` Thierry Reding
2020-11-10 18:27 ` Marc Zyngier
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