From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BA4AC433E7 for ; Mon, 19 Oct 2020 06:18:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C9C9C22276 for ; Mon, 19 Oct 2020 06:18:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726755AbgJSGSs (ORCPT ); Mon, 19 Oct 2020 02:18:48 -0400 Received: from mga17.intel.com ([192.55.52.151]:53114 "EHLO mga17.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726724AbgJSGSp (ORCPT ); Mon, 19 Oct 2020 02:18:45 -0400 IronPort-SDR: BxF1mBO/P/M1GF1pomsvn10GEaCdgtJk8qzm94a6y0faI+CnjIaplSNMCC8xE8oN1IZPFzC/Pc uZYaHY01+2Kg== X-IronPort-AV: E=McAfee;i="6000,8403,9778"; a="146835895" X-IronPort-AV: E=Sophos;i="5.77,393,1596524400"; d="scan'208";a="146835895" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2020 23:18:45 -0700 IronPort-SDR: DOOwrRxhlREUnfzF3P4fBwkTL1xx19kF8mup+GPAhbAfIsxq052ClY1rm8MR3KvikhGbQulU7W N7N6TS/K9erw== X-IronPort-AV: E=Sophos;i="5.77,393,1596524400"; d="scan'208";a="320159384" Received: from shsi6026.sh.intel.com (HELO localhost) ([10.239.147.88]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2020 23:18:38 -0700 From: shuo.a.liu@intel.com To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Greg Kroah-Hartman , "H . Peter Anvin" , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Sean Christopherson , Yu Wang , Reinette Chatre , Shuo Liu , Yakui Zhao , Dave Hansen , Dan Williams , Fengwei Yin , Zhi Wang , Zhenyu Wang , Arvind Sankar , Peter Zijlstra , Nick Desaulniers , Segher Boessenkool Subject: [PATCH v5 04/17] x86/acrn: Introduce hypercall interfaces Date: Mon, 19 Oct 2020 14:17:50 +0800 Message-Id: <20201019061803.13298-5-shuo.a.liu@intel.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201019061803.13298-1-shuo.a.liu@intel.com> References: <20201019061803.13298-1-shuo.a.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Shuo Liu The Service VM communicates with the hypervisor via conventional hypercalls. VMCALL instruction is used to make the hypercalls. ACRN hypercall ABI: * Hypercall number is in R8 register. * Up to 2 parameters are in RDI and RSI registers. * Return value is in RAX register. Introduce the ACRN hypercall interfaces. Because GCC doesn't support R8 register as direct register constraints, use supported constraint as input with a explicit MOV to R8 in beginning of asm. Originally-by: Yakui Zhao Signed-off-by: Shuo Liu Reviewed-by: Reinette Chatre Cc: Dave Hansen Cc: Sean Christopherson Cc: Dan Williams Cc: Fengwei Yin Cc: Zhi Wang Cc: Zhenyu Wang Cc: Yu Wang Cc: Reinette Chatre Cc: Greg Kroah-Hartman Cc: Borislav Petkov Cc: Arvind Sankar Cc: Peter Zijlstra Cc: Nick Desaulniers Cc: Segher Boessenkool --- arch/x86/include/asm/acrn.h | 54 +++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/x86/include/asm/acrn.h b/arch/x86/include/asm/acrn.h index a2d4aea3a80d..03e420245505 100644 --- a/arch/x86/include/asm/acrn.h +++ b/arch/x86/include/asm/acrn.h @@ -14,4 +14,58 @@ void acrn_setup_intr_handler(void (*handler)(void)); void acrn_remove_intr_handler(void); bool acrn_is_privileged_vm(void); +/* + * Hypercalls for ACRN + * + * - VMCALL instruction is used to implement ACRN hypercalls. + * - ACRN hypercall ABI: + * - Hypercall number is passed in R8 register. + * - Up to 2 arguments are passed in RDI, RSI. + * - Return value will be placed in RAX. + * + * Because GCC doesn't support R8 register as direct register constraints, use + * supported constraint as input with a explicit MOV to R8 in beginning of asm. + */ +static inline long acrn_hypercall0(unsigned long hcall_id) +{ + long result; + + asm volatile("movl %1, %%r8d\n\t" + "vmcall\n\t" + : "=a" (result) + : "ir" (hcall_id) + : "r8", "memory"); + + return result; +} + +static inline long acrn_hypercall1(unsigned long hcall_id, + unsigned long param1) +{ + long result; + + asm volatile("movl %1, %%r8d\n\t" + "vmcall\n\t" + : "=a" (result) + : "ir" (hcall_id), "D" (param1) + : "r8", "memory"); + + return result; +} + +static inline long acrn_hypercall2(unsigned long hcall_id, + unsigned long param1, + unsigned long param2) +{ + long result; + + asm volatile("movl %1, %%r8d\n\t" + "vmcall\n\t" + : "=a" (result) + : "ir" (hcall_id), "D" (param1), "S" (param2) + : "r8", "memory"); + + return result; +} + #endif /* _ASM_X86_ACRN_H */ -- 2.28.0