* [PATCH v2 1/6] dt-bindings: pci: drop samsung,exynos5440-pcie binding
2020-10-23 7:57 ` [PATCH v2 0/6] Add DW PCIe support for Exynos5433 SoCs Marek Szyprowski
@ 2020-10-23 7:57 ` Marek Szyprowski
2020-10-24 2:59 ` Jingoo Han
2020-10-23 7:57 ` [PATCH v2 2/6] dt-bindings: pci: add the samsung,exynos-pcie binding Marek Szyprowski
` (4 subsequent siblings)
5 siblings, 1 reply; 20+ messages in thread
From: Marek Szyprowski @ 2020-10-23 7:57 UTC (permalink / raw)
To: linux-samsung-soc, linux-pci
Cc: devicetree, linux-kernel, Jaehoon Chung, Marek Szyprowski,
Jingoo Han, Krzysztof Kozlowski, Bjorn Helgaas, Lorenzo Pieralisi,
Vinod Koul, Kishon Vijay Abraham I, Rob Herring
Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM:
dts: exynos: Remove Exynos5440"). Drop the obsolete bindings for
exynos5440-pcie.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
---
.../bindings/pci/samsung,exynos5440-pcie.txt | 58 -------------------
1 file changed, 58 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
deleted file mode 100644
index 651d957d1051..000000000000
--- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-* Samsung Exynos 5440 PCIe interface
-
-This PCIe host controller is based on the Synopsys DesignWare PCIe IP
-and thus inherits all the common properties defined in designware-pcie.txt.
-
-Required properties:
-- compatible: "samsung,exynos5440-pcie"
-- reg: base addresses and lengths of the PCIe controller,
-- reg-names : First name should be set to "elbi".
- And use the "config" instead of getting the configuration address space
- from "ranges".
- NOTE: When using the "config" property, reg-names must be set.
-- interrupts: A list of interrupt outputs for level interrupt,
- pulse interrupt, special interrupt.
-- phys: From PHY binding. Phandle for the generic PHY.
- Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt
-
-For other common properties, refer to
- Documentation/devicetree/bindings/pci/designware-pcie.txt
-
-Example:
-
-SoC-specific DT Entry (with using PHY framework):
-
- pcie_phy0: pcie-phy@270000 {
- ...
- reg = <0x270000 0x1000>, <0x271000 0x40>;
- reg-names = "phy", "block";
- ...
- };
-
- pcie@290000 {
- compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
- reg = <0x290000 0x1000>, <0x40000000 0x1000>;
- reg-names = "elbi", "config";
- clocks = <&clock 28>, <&clock 27>;
- clock-names = "pcie", "pcie_bus";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- phys = <&pcie_phy0>;
- ranges = <0x81000000 0 0 0x60001000 0 0x00010000
- 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- num-lanes = <4>;
- };
-
-Board-specific DT Entry:
-
- pcie@290000 {
- reset-gpio = <&pin_ctrl 5 0>;
- };
-
- pcie@2a0000 {
- reset-gpio = <&pin_ctrl 22 0>;
- };
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v2 1/6] dt-bindings: pci: drop samsung,exynos5440-pcie binding
2020-10-23 7:57 ` [PATCH v2 1/6] dt-bindings: pci: drop samsung,exynos5440-pcie binding Marek Szyprowski
@ 2020-10-24 2:59 ` Jingoo Han
0 siblings, 0 replies; 20+ messages in thread
From: Jingoo Han @ 2020-10-24 2:59 UTC (permalink / raw)
To: Marek Szyprowski, linux-samsung-soc@vger.kernel.org,
linux-pci@vger.kernel.org
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Jaehoon Chung, Krzysztof Kozlowski, Bjorn Helgaas,
Lorenzo Pieralisi, Vinod Koul, Kishon Vijay Abraham I,
Rob Herring, Han Jingoo
On 10/23/20, 3:58 AM, Marek Szyprowski wrote:
>
> Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM:
> dts: exynos: Remove Exynos5440"). Drop the obsolete bindings for
> exynos5440-pcie.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Jingoo Han <jingoohan1@gmail.com>
Best regards,
Jingoo Han
> ---
> .../bindings/pci/samsung,exynos5440-pcie.txt | 58 -------------------
> 1 file changed, 58 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
[.....]
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 2/6] dt-bindings: pci: add the samsung,exynos-pcie binding
2020-10-23 7:57 ` [PATCH v2 0/6] Add DW PCIe support for Exynos5433 SoCs Marek Szyprowski
2020-10-23 7:57 ` [PATCH v2 1/6] dt-bindings: pci: drop samsung,exynos5440-pcie binding Marek Szyprowski
@ 2020-10-23 7:57 ` Marek Szyprowski
2020-10-23 9:26 ` Krzysztof Kozlowski
2020-10-23 7:57 ` [PATCH v2 3/6] dt-bindings: phy: add the samsung,exynos-pcie-phy binding Marek Szyprowski
` (3 subsequent siblings)
5 siblings, 1 reply; 20+ messages in thread
From: Marek Szyprowski @ 2020-10-23 7:57 UTC (permalink / raw)
To: linux-samsung-soc, linux-pci
Cc: devicetree, linux-kernel, Jaehoon Chung, Marek Szyprowski,
Jingoo Han, Krzysztof Kozlowski, Bjorn Helgaas, Lorenzo Pieralisi,
Vinod Koul, Kishon Vijay Abraham I, Rob Herring
Add dt-bindings for the Samsung Exynos PCIe controller (Exynos5433
variant). Based on the text dt-binding posted by Jaehoon Chung.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
.../bindings/pci/samsung,exynos-pcie.yaml | 114 ++++++++++++++++++
1 file changed, 114 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
new file mode 100644
index 000000000000..6ddba0cb400e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
@@ -0,0 +1,114 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SoC series PCIe Host Controller Device Tree Bindings
+
+maintainers:
+ - Marek Szyprowski <m.szyprowski@samsung.com>
+ - Jaehoon Chung <jh80.chung@samsung.com>
+
+description: |+
+ Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare
+ PCIe IP and thus inherits all the common properties defined in
+ designware-pcie.txt.
+
+allOf:
+ - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+ compatible:
+ const: samsung,exynos5433-pcie
+
+ reg:
+ items:
+ - description: Data Bus Interface (DBI) registers.
+ - description: External Local Bus interface (ELBI) registers.
+ - description: PCIe configuration space region.
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: elbi
+ - const: config
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: PCIe bridge clock
+ - description: PCIe bus clock
+
+ clock-names:
+ items:
+ - const: pcie
+ - const: pcie_bus
+
+ phys:
+ maxItems: 1
+
+ vdd10-supply:
+ description:
+ Phandle to a regulator that provides 1.0V power to the PCIe block.
+
+ vdd18-supply:
+ description:
+ Phandle to a regulator that provides 1.8V power to the PCIe block.
+
+ num-lanes:
+ const: 1
+
+required:
+ - reg
+ - reg-names
+ - interrupts
+ - "#address-cells"
+ - "#size-cells"
+ - "#interrupt-cells"
+ - interrupt-map
+ - interrupt-map-mask
+ - ranges
+ - bus-range
+ - device_type
+ - num-lanes
+ - clocks
+ - clock-names
+ - phys
+ - vdd10-supply
+ - vdd18-supply
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/exynos5433.h>
+
+ pcie: pcie@15700000 {
+ compatible = "samsung,exynos5433-pcie";
+ reg = <0x15700000 0x1000>, <0x156b0000 0x1000>, <0x0c000000 0x1000>;
+ reg-names = "dbi", "elbi", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>;
+ clock-names = "pcie", "pcie_bus";
+ phys = <&pcie_phy>;
+ pinctrl-0 = <&pcie_bus &pcie_wlanen>;
+ pinctrl-names = "default";
+ num-lanes = <1>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>,
+ <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>;
+ vdd10-supply = <&ldo6_reg>;
+ vdd18-supply = <&ldo7_reg>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
+ };
+...
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v2 2/6] dt-bindings: pci: add the samsung,exynos-pcie binding
2020-10-23 7:57 ` [PATCH v2 2/6] dt-bindings: pci: add the samsung,exynos-pcie binding Marek Szyprowski
@ 2020-10-23 9:26 ` Krzysztof Kozlowski
0 siblings, 0 replies; 20+ messages in thread
From: Krzysztof Kozlowski @ 2020-10-23 9:26 UTC (permalink / raw)
To: Marek Szyprowski
Cc: linux-samsung-soc, linux-pci, devicetree, linux-kernel,
Jaehoon Chung, Jingoo Han, Bjorn Helgaas, Lorenzo Pieralisi,
Vinod Koul, Kishon Vijay Abraham I, Rob Herring
On Fri, Oct 23, 2020 at 09:57:40AM +0200, Marek Szyprowski wrote:
> Add dt-bindings for the Samsung Exynos PCIe controller (Exynos5433
> variant). Based on the text dt-binding posted by Jaehoon Chung.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
> .../bindings/pci/samsung,exynos-pcie.yaml | 114 ++++++++++++++++++
> 1 file changed, 114 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 3/6] dt-bindings: phy: add the samsung,exynos-pcie-phy binding
2020-10-23 7:57 ` [PATCH v2 0/6] Add DW PCIe support for Exynos5433 SoCs Marek Szyprowski
2020-10-23 7:57 ` [PATCH v2 1/6] dt-bindings: pci: drop samsung,exynos5440-pcie binding Marek Szyprowski
2020-10-23 7:57 ` [PATCH v2 2/6] dt-bindings: pci: add the samsung,exynos-pcie binding Marek Szyprowski
@ 2020-10-23 7:57 ` Marek Szyprowski
2020-10-23 9:28 ` Krzysztof Kozlowski
2020-10-23 7:57 ` [PATCH v2 4/6] phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433 PCIe PHY Marek Szyprowski
` (2 subsequent siblings)
5 siblings, 1 reply; 20+ messages in thread
From: Marek Szyprowski @ 2020-10-23 7:57 UTC (permalink / raw)
To: linux-samsung-soc, linux-pci
Cc: devicetree, linux-kernel, Jaehoon Chung, Marek Szyprowski,
Jingoo Han, Krzysztof Kozlowski, Bjorn Helgaas, Lorenzo Pieralisi,
Vinod Koul, Kishon Vijay Abraham I, Rob Herring
Add dt-bindings for the Samsung Exynos PCIe PHY controller (Exynos5433
variant). Based on the text dt-binding posted by Jaehoon Chung.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
.../bindings/phy/samsung,exynos-pcie-phy.yaml | 51 +++++++++++++++++++
1 file changed, 51 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml
new file mode 100644
index 000000000000..ac0af40be52d
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/samsung,exynos-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SoC series PCIe PHY Device Tree Bindings
+
+maintainers:
+ - Marek Szyprowski <m.szyprowski@samsung.com>
+ - Jaehoon Chung <jh80.chung@samsung.com>
+
+properties:
+ "#phy-cells":
+ const: 0
+
+ compatible:
+ const: samsung,exynos5433-pcie-phy
+
+ reg:
+ maxItems: 1
+
+ samsung,pmu-syscon:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: phandle for PMU system controller interface, used to
+ control PMU registers bits for PCIe PHY
+
+ samsung,fsys-sysreg:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: phandle for FSYS sysreg interface, used to control
+ sysreg registers bits for PCIe PHY
+
+required:
+ - "#phy-cells"
+ - compatible
+ - reg
+ - samsung,pmu-syscon
+ - samsung,fsys-sysreg
+
+additionalProperties: false
+
+examples:
+ - |
+ pcie_phy: pcie-phy@15680000 {
+ compatible = "samsung,exynos5433-pcie-phy";
+ reg = <0x15680000 0x1000>;
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ samsung,fsys-sysreg = <&syscon_fsys>;
+ #phy-cells = <0>;
+ };
+...
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v2 3/6] dt-bindings: phy: add the samsung,exynos-pcie-phy binding
2020-10-23 7:57 ` [PATCH v2 3/6] dt-bindings: phy: add the samsung,exynos-pcie-phy binding Marek Szyprowski
@ 2020-10-23 9:28 ` Krzysztof Kozlowski
0 siblings, 0 replies; 20+ messages in thread
From: Krzysztof Kozlowski @ 2020-10-23 9:28 UTC (permalink / raw)
To: Marek Szyprowski
Cc: linux-samsung-soc, linux-pci, devicetree, linux-kernel,
Jaehoon Chung, Jingoo Han, Bjorn Helgaas, Lorenzo Pieralisi,
Vinod Koul, Kishon Vijay Abraham I, Rob Herring
On Fri, Oct 23, 2020 at 09:57:41AM +0200, Marek Szyprowski wrote:
> Add dt-bindings for the Samsung Exynos PCIe PHY controller (Exynos5433
> variant). Based on the text dt-binding posted by Jaehoon Chung.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
> .../bindings/phy/samsung,exynos-pcie-phy.yaml | 51 +++++++++++++++++++
> 1 file changed, 51 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml
>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 4/6] phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433 PCIe PHY
2020-10-23 7:57 ` [PATCH v2 0/6] Add DW PCIe support for Exynos5433 SoCs Marek Szyprowski
` (2 preceding siblings ...)
2020-10-23 7:57 ` [PATCH v2 3/6] dt-bindings: phy: add the samsung,exynos-pcie-phy binding Marek Szyprowski
@ 2020-10-23 7:57 ` Marek Szyprowski
2020-10-24 3:00 ` Jingoo Han
2020-10-26 18:50 ` Rob Herring
2020-10-23 7:57 ` [PATCH v2 5/6] pci: dwc: pci-exynos: rework the driver to support Exynos5433 variant Marek Szyprowski
2020-10-23 7:57 ` [PATCH v2 6/6] arm64: dts: exynos: add the WiFi/PCIe support to TM2(e) boards Marek Szyprowski
5 siblings, 2 replies; 20+ messages in thread
From: Marek Szyprowski @ 2020-10-23 7:57 UTC (permalink / raw)
To: linux-samsung-soc, linux-pci
Cc: devicetree, linux-kernel, Jaehoon Chung, Marek Szyprowski,
Jingoo Han, Krzysztof Kozlowski, Bjorn Helgaas, Lorenzo Pieralisi,
Vinod Koul, Kishon Vijay Abraham I, Rob Herring
From: Jaehoon Chung <jh80.chung@samsung.com>
Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM:
dts: exynos: Remove Exynos5440"). Rework this driver to support PCIe PHY
variant found in the Exynos5433 SoCs.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
[mszyprow: reworked the driver to support only Exynos5433 variant, rebased
onto current kernel code, rewrote commit message]
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
---
drivers/phy/samsung/phy-exynos-pcie.c | 304 ++++++++++----------------
1 file changed, 112 insertions(+), 192 deletions(-)
diff --git a/drivers/phy/samsung/phy-exynos-pcie.c b/drivers/phy/samsung/phy-exynos-pcie.c
index 7e28b1aea0d1..d91de323dd0e 100644
--- a/drivers/phy/samsung/phy-exynos-pcie.c
+++ b/drivers/phy/samsung/phy-exynos-pcie.c
@@ -4,70 +4,41 @@
*
* Phy provider for PCIe controller on Exynos SoC series
*
- * Copyright (C) 2017 Samsung Electronics Co., Ltd.
+ * Copyright (C) 2017-2020 Samsung Electronics Co., Ltd.
* Jaehoon Chung <jh80.chung@samsung.com>
*/
-#include <linux/delay.h>
#include <linux/io.h>
-#include <linux/iopoll.h>
-#include <linux/init.h>
#include <linux/mfd/syscon.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/phy/phy.h>
#include <linux/regmap.h>
-/* PCIe Purple registers */
-#define PCIE_PHY_GLOBAL_RESET 0x000
-#define PCIE_PHY_COMMON_RESET 0x004
-#define PCIE_PHY_CMN_REG 0x008
-#define PCIE_PHY_MAC_RESET 0x00c
-#define PCIE_PHY_PLL_LOCKED 0x010
-#define PCIE_PHY_TRSVREG_RESET 0x020
-#define PCIE_PHY_TRSV_RESET 0x024
-
-/* PCIe PHY registers */
-#define PCIE_PHY_IMPEDANCE 0x004
-#define PCIE_PHY_PLL_DIV_0 0x008
-#define PCIE_PHY_PLL_BIAS 0x00c
-#define PCIE_PHY_DCC_FEEDBACK 0x014
-#define PCIE_PHY_PLL_DIV_1 0x05c
-#define PCIE_PHY_COMMON_POWER 0x064
-#define PCIE_PHY_COMMON_PD_CMN BIT(3)
-#define PCIE_PHY_TRSV0_EMP_LVL 0x084
-#define PCIE_PHY_TRSV0_DRV_LVL 0x088
-#define PCIE_PHY_TRSV0_RXCDR 0x0ac
-#define PCIE_PHY_TRSV0_POWER 0x0c4
-#define PCIE_PHY_TRSV0_PD_TSV BIT(7)
-#define PCIE_PHY_TRSV0_LVCC 0x0dc
-#define PCIE_PHY_TRSV1_EMP_LVL 0x144
-#define PCIE_PHY_TRSV1_RXCDR 0x16c
-#define PCIE_PHY_TRSV1_POWER 0x184
-#define PCIE_PHY_TRSV1_PD_TSV BIT(7)
-#define PCIE_PHY_TRSV1_LVCC 0x19c
-#define PCIE_PHY_TRSV2_EMP_LVL 0x204
-#define PCIE_PHY_TRSV2_RXCDR 0x22c
-#define PCIE_PHY_TRSV2_POWER 0x244
-#define PCIE_PHY_TRSV2_PD_TSV BIT(7)
-#define PCIE_PHY_TRSV2_LVCC 0x25c
-#define PCIE_PHY_TRSV3_EMP_LVL 0x2c4
-#define PCIE_PHY_TRSV3_RXCDR 0x2ec
-#define PCIE_PHY_TRSV3_POWER 0x304
-#define PCIE_PHY_TRSV3_PD_TSV BIT(7)
-#define PCIE_PHY_TRSV3_LVCC 0x31c
-
-struct exynos_pcie_phy_data {
- const struct phy_ops *ops;
-};
+#define PCIE_PHY_OFFSET(x) ((x) * 0x4)
+
+/* Sysreg FSYS register offsets and bits for Exynos5433 */
+#define PCIE_EXYNOS5433_PHY_MAC_RESET 0x0208
+#define PCIE_MAC_RESET_MASK 0xFF
+#define PCIE_MAC_RESET BIT(4)
+#define PCIE_EXYNOS5433_PHY_L1SUB_CM_CON 0x1010
+#define PCIE_REFCLK_GATING_EN BIT(0)
+#define PCIE_EXYNOS5433_PHY_COMMON_RESET 0x1020
+#define PCIE_PHY_RESET BIT(0)
+#define PCIE_EXYNOS5433_PHY_GLOBAL_RESET 0x1040
+#define PCIE_GLOBAL_RESET BIT(0)
+#define PCIE_REFCLK BIT(1)
+#define PCIE_REFCLK_MASK 0x16
+#define PCIE_APP_REQ_EXIT_L1_MODE BIT(5)
+
+/* PMU PCIE PHY isolation control */
+#define EXYNOS5433_PMU_PCIE_PHY_OFFSET 0x730
/* For Exynos pcie phy */
struct exynos_pcie_phy {
- const struct exynos_pcie_phy_data *drv_data;
- void __iomem *phy_base;
- void __iomem *blk_base; /* For exynos5440 */
+ void __iomem *base;
+ struct regmap *pmureg;
+ struct regmap *fsysreg;
};
static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset)
@@ -75,153 +46,103 @@ static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset)
writel(val, base + offset);
}
-static u32 exynos_pcie_phy_readl(void __iomem *base, u32 offset)
-{
- return readl(base + offset);
-}
-
-/* For Exynos5440 specific functions */
-static int exynos5440_pcie_phy_init(struct phy *phy)
+/* Exynos5433 specific functions */
+static int exynos5433_pcie_phy_init(struct phy *phy)
{
struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
- /* DCC feedback control off */
- exynos_pcie_phy_writel(ep->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK);
-
- /* set TX/RX impedance */
- exynos_pcie_phy_writel(ep->phy_base, 0xd5, PCIE_PHY_IMPEDANCE);
-
- /* set 50Mhz PHY clock */
- exynos_pcie_phy_writel(ep->phy_base, 0x14, PCIE_PHY_PLL_DIV_0);
- exynos_pcie_phy_writel(ep->phy_base, 0x12, PCIE_PHY_PLL_DIV_1);
-
- /* set TX Differential output for lane 0 */
- exynos_pcie_phy_writel(ep->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
-
- /* set TX Pre-emphasis Level Control for lane 0 to minimum */
- exynos_pcie_phy_writel(ep->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
-
- /* set RX clock and data recovery bandwidth */
- exynos_pcie_phy_writel(ep->phy_base, 0xe7, PCIE_PHY_PLL_BIAS);
- exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR);
- exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR);
- exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV2_RXCDR);
- exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV3_RXCDR);
-
- /* change TX Pre-emphasis Level Control for lanes */
- exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
- exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
- exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
- exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
-
- /* set LVCC */
- exynos_pcie_phy_writel(ep->phy_base, 0x20, PCIE_PHY_TRSV0_LVCC);
- exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV1_LVCC);
- exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV2_LVCC);
- exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV3_LVCC);
-
- /* pulse for common reset */
- exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_COMMON_RESET);
- udelay(500);
- exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
-
+ regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_COMMON_RESET,
+ PCIE_PHY_RESET, 1);
+ regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_MAC_RESET,
+ PCIE_MAC_RESET, 0);
+
+ /* PHY refclk 24MHz */
+ regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET,
+ PCIE_REFCLK_MASK, PCIE_REFCLK);
+ regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET,
+ PCIE_GLOBAL_RESET, 0);
+
+
+ exynos_pcie_phy_writel(ep->base, 0x11, PCIE_PHY_OFFSET(0x3));
+
+ /* band gap reference on */
+ exynos_pcie_phy_writel(ep->base, 0, PCIE_PHY_OFFSET(0x20));
+ exynos_pcie_phy_writel(ep->base, 0, PCIE_PHY_OFFSET(0x4b));
+
+ /* jitter tunning */
+ exynos_pcie_phy_writel(ep->base, 0x34, PCIE_PHY_OFFSET(0x4));
+ exynos_pcie_phy_writel(ep->base, 0x02, PCIE_PHY_OFFSET(0x7));
+ exynos_pcie_phy_writel(ep->base, 0x41, PCIE_PHY_OFFSET(0x21));
+ exynos_pcie_phy_writel(ep->base, 0x7F, PCIE_PHY_OFFSET(0x14));
+ exynos_pcie_phy_writel(ep->base, 0xC0, PCIE_PHY_OFFSET(0x15));
+ exynos_pcie_phy_writel(ep->base, 0x61, PCIE_PHY_OFFSET(0x36));
+
+ /* D0 uninit.. */
+ exynos_pcie_phy_writel(ep->base, 0x44, PCIE_PHY_OFFSET(0x3D));
+
+ /* 24MHz */
+ exynos_pcie_phy_writel(ep->base, 0x94, PCIE_PHY_OFFSET(0x8));
+ exynos_pcie_phy_writel(ep->base, 0xA7, PCIE_PHY_OFFSET(0x9));
+ exynos_pcie_phy_writel(ep->base, 0x93, PCIE_PHY_OFFSET(0xA));
+ exynos_pcie_phy_writel(ep->base, 0x6B, PCIE_PHY_OFFSET(0xC));
+ exynos_pcie_phy_writel(ep->base, 0xA5, PCIE_PHY_OFFSET(0xF));
+ exynos_pcie_phy_writel(ep->base, 0x34, PCIE_PHY_OFFSET(0x16));
+ exynos_pcie_phy_writel(ep->base, 0xA3, PCIE_PHY_OFFSET(0x17));
+ exynos_pcie_phy_writel(ep->base, 0xA7, PCIE_PHY_OFFSET(0x1A));
+ exynos_pcie_phy_writel(ep->base, 0x71, PCIE_PHY_OFFSET(0x23));
+ exynos_pcie_phy_writel(ep->base, 0x4C, PCIE_PHY_OFFSET(0x24));
+
+ exynos_pcie_phy_writel(ep->base, 0x0E, PCIE_PHY_OFFSET(0x26));
+ exynos_pcie_phy_writel(ep->base, 0x14, PCIE_PHY_OFFSET(0x7));
+ exynos_pcie_phy_writel(ep->base, 0x48, PCIE_PHY_OFFSET(0x43));
+ exynos_pcie_phy_writel(ep->base, 0x44, PCIE_PHY_OFFSET(0x44));
+ exynos_pcie_phy_writel(ep->base, 0x03, PCIE_PHY_OFFSET(0x45));
+ exynos_pcie_phy_writel(ep->base, 0xA7, PCIE_PHY_OFFSET(0x48));
+ exynos_pcie_phy_writel(ep->base, 0x13, PCIE_PHY_OFFSET(0x54));
+ exynos_pcie_phy_writel(ep->base, 0x04, PCIE_PHY_OFFSET(0x31));
+ exynos_pcie_phy_writel(ep->base, 0, PCIE_PHY_OFFSET(0x32));
+
+ regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_COMMON_RESET,
+ PCIE_PHY_RESET, 0);
+ regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_MAC_RESET,
+ PCIE_MAC_RESET_MASK, PCIE_MAC_RESET);
return 0;
}
-static int exynos5440_pcie_phy_power_on(struct phy *phy)
+static int exynos5433_pcie_phy_power_on(struct phy *phy)
{
struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
- u32 val;
-
- exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
- exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_CMN_REG);
- exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSVREG_RESET);
- exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSV_RESET);
-
- val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
- val &= ~PCIE_PHY_COMMON_PD_CMN;
- exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
-
- val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
- val &= ~PCIE_PHY_TRSV0_PD_TSV;
- exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
-
- val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
- val &= ~PCIE_PHY_TRSV1_PD_TSV;
- exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
-
- val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
- val &= ~PCIE_PHY_TRSV2_PD_TSV;
- exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
-
- val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
- val &= ~PCIE_PHY_TRSV3_PD_TSV;
- exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
+ regmap_update_bits(ep->pmureg, EXYNOS5433_PMU_PCIE_PHY_OFFSET,
+ BIT(0), 1);
+ regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET,
+ PCIE_APP_REQ_EXIT_L1_MODE, 0);
+ regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_L1SUB_CM_CON,
+ PCIE_REFCLK_GATING_EN, 0);
return 0;
}
-static int exynos5440_pcie_phy_power_off(struct phy *phy)
+static int exynos5433_pcie_phy_power_off(struct phy *phy)
{
struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
- u32 val;
-
- if (readl_poll_timeout(ep->phy_base + PCIE_PHY_PLL_LOCKED, val,
- (val != 0), 1, 500)) {
- dev_err(&phy->dev, "PLL Locked: 0x%x\n", val);
- return -ETIMEDOUT;
- }
-
- val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
- val |= PCIE_PHY_COMMON_PD_CMN;
- exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
-
- val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
- val |= PCIE_PHY_TRSV0_PD_TSV;
- exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
-
- val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
- val |= PCIE_PHY_TRSV1_PD_TSV;
- exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
-
- val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
- val |= PCIE_PHY_TRSV2_PD_TSV;
- exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
-
- val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
- val |= PCIE_PHY_TRSV3_PD_TSV;
- exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
+ regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_L1SUB_CM_CON,
+ PCIE_REFCLK_GATING_EN, PCIE_REFCLK_GATING_EN);
+ regmap_update_bits(ep->pmureg, EXYNOS5433_PMU_PCIE_PHY_OFFSET,
+ BIT(0), 0);
return 0;
}
-static int exynos5440_pcie_phy_reset(struct phy *phy)
-{
- struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
-
- exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_MAC_RESET);
- exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_GLOBAL_RESET);
- exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_GLOBAL_RESET);
-
- return 0;
-}
-
-static const struct phy_ops exynos5440_phy_ops = {
- .init = exynos5440_pcie_phy_init,
- .power_on = exynos5440_pcie_phy_power_on,
- .power_off = exynos5440_pcie_phy_power_off,
- .reset = exynos5440_pcie_phy_reset,
+static const struct phy_ops exynos5433_phy_ops = {
+ .init = exynos5433_pcie_phy_init,
+ .power_on = exynos5433_pcie_phy_power_on,
+ .power_off = exynos5433_pcie_phy_power_off,
.owner = THIS_MODULE,
};
-static const struct exynos_pcie_phy_data exynos5440_pcie_phy_data = {
- .ops = &exynos5440_phy_ops,
-};
-
static const struct of_device_id exynos_pcie_phy_match[] = {
{
- .compatible = "samsung,exynos5440-pcie-phy",
- .data = &exynos5440_pcie_phy_data,
+ .compatible = "samsung,exynos5433-pcie-phy",
},
{},
};
@@ -232,30 +153,30 @@ static int exynos_pcie_phy_probe(struct platform_device *pdev)
struct exynos_pcie_phy *exynos_phy;
struct phy *generic_phy;
struct phy_provider *phy_provider;
- struct resource *res;
- const struct exynos_pcie_phy_data *drv_data;
-
- drv_data = of_device_get_match_data(dev);
- if (!drv_data)
- return -ENODEV;
exynos_phy = devm_kzalloc(dev, sizeof(*exynos_phy), GFP_KERNEL);
if (!exynos_phy)
return -ENOMEM;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- exynos_phy->phy_base = devm_ioremap_resource(dev, res);
- if (IS_ERR(exynos_phy->phy_base))
- return PTR_ERR(exynos_phy->phy_base);
+ exynos_phy->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(exynos_phy->base))
+ return PTR_ERR(exynos_phy->base);
- res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- exynos_phy->blk_base = devm_ioremap_resource(dev, res);
- if (IS_ERR(exynos_phy->blk_base))
- return PTR_ERR(exynos_phy->blk_base);
+ exynos_phy->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
+ "samsung,pmu-syscon");
+ if (IS_ERR(exynos_phy->pmureg)) {
+ dev_err(&pdev->dev, "PMU regmap lookup failed.\n");
+ return PTR_ERR(exynos_phy->pmureg);
+ }
- exynos_phy->drv_data = drv_data;
+ exynos_phy->fsysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
+ "samsung,fsys-sysreg");
+ if (IS_ERR(exynos_phy->fsysreg)) {
+ dev_err(&pdev->dev, "FSYS sysreg regmap lookup failed.\n");
+ return PTR_ERR(exynos_phy->fsysreg);
+ }
- generic_phy = devm_phy_create(dev, dev->of_node, drv_data->ops);
+ generic_phy = devm_phy_create(dev, dev->of_node, &exynos5433_phy_ops);
if (IS_ERR(generic_phy)) {
dev_err(dev, "failed to create PHY\n");
return PTR_ERR(generic_phy);
@@ -275,5 +196,4 @@ static struct platform_driver exynos_pcie_phy_driver = {
.suppress_bind_attrs = true,
}
};
-
builtin_platform_driver(exynos_pcie_phy_driver);
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v2 4/6] phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433 PCIe PHY
2020-10-23 7:57 ` [PATCH v2 4/6] phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433 PCIe PHY Marek Szyprowski
@ 2020-10-24 3:00 ` Jingoo Han
2020-10-26 18:50 ` Rob Herring
1 sibling, 0 replies; 20+ messages in thread
From: Jingoo Han @ 2020-10-24 3:00 UTC (permalink / raw)
To: Marek Szyprowski, linux-samsung-soc@vger.kernel.org,
linux-pci@vger.kernel.org
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Jaehoon Chung, Krzysztof Kozlowski, Bjorn Helgaas,
Lorenzo Pieralisi, Vinod Koul, Kishon Vijay Abraham I,
Rob Herring, Han Jingoo
On 10/23/20, 3:59 AM, Marek Szyprowski wrote:
>
> From: Jaehoon Chung <jh80.chung@samsung.com>
>
> Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM:
> dts: exynos: Remove Exynos5440"). Rework this driver to support PCIe PHY
> variant found in the Exynos5433 SoCs.
>
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
> [mszyprow: reworked the driver to support only Exynos5433 variant, rebased
> onto current kernel code, rewrote commit message]
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
>
Reviewed-by: Jingoo Han <jingoohan1@gmail.com>
Best regards,
Jingoo Han
> ---
> drivers/phy/samsung/phy-exynos-pcie.c | 304 ++++++++++----------------
> 1 file changed, 112 insertions(+), 192 deletions(-)
[.....]
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v2 4/6] phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433 PCIe PHY
2020-10-23 7:57 ` [PATCH v2 4/6] phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433 PCIe PHY Marek Szyprowski
2020-10-24 3:00 ` Jingoo Han
@ 2020-10-26 18:50 ` Rob Herring
2020-10-27 12:28 ` Marek Szyprowski
1 sibling, 1 reply; 20+ messages in thread
From: Rob Herring @ 2020-10-26 18:50 UTC (permalink / raw)
To: Marek Szyprowski
Cc: linux-samsung-soc, PCI, devicetree, linux-kernel@vger.kernel.org,
Jaehoon Chung, Jingoo Han, Krzysztof Kozlowski, Bjorn Helgaas,
Lorenzo Pieralisi, Vinod Koul, Kishon Vijay Abraham I
On Fri, Oct 23, 2020 at 2:58 AM Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
>
> From: Jaehoon Chung <jh80.chung@samsung.com>
>
> Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM:
> dts: exynos: Remove Exynos5440"). Rework this driver to support PCIe PHY
> variant found in the Exynos5433 SoCs.
>
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
> [mszyprow: reworked the driver to support only Exynos5433 variant, rebased
> onto current kernel code, rewrote commit message]
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
> drivers/phy/samsung/phy-exynos-pcie.c | 304 ++++++++++----------------
> 1 file changed, 112 insertions(+), 192 deletions(-)
>
> diff --git a/drivers/phy/samsung/phy-exynos-pcie.c b/drivers/phy/samsung/phy-exynos-pcie.c
> index 7e28b1aea0d1..d91de323dd0e 100644
> --- a/drivers/phy/samsung/phy-exynos-pcie.c
> +++ b/drivers/phy/samsung/phy-exynos-pcie.c
> @@ -4,70 +4,41 @@
> *
> * Phy provider for PCIe controller on Exynos SoC series
> *
> - * Copyright (C) 2017 Samsung Electronics Co., Ltd.
> + * Copyright (C) 2017-2020 Samsung Electronics Co., Ltd.
> * Jaehoon Chung <jh80.chung@samsung.com>
> */
>
> -#include <linux/delay.h>
> #include <linux/io.h>
> -#include <linux/iopoll.h>
> -#include <linux/init.h>
> #include <linux/mfd/syscon.h>
> -#include <linux/of.h>
> -#include <linux/of_address.h>
> #include <linux/of_platform.h>
> #include <linux/platform_device.h>
> #include <linux/phy/phy.h>
> #include <linux/regmap.h>
>
> -/* PCIe Purple registers */
> -#define PCIE_PHY_GLOBAL_RESET 0x000
> -#define PCIE_PHY_COMMON_RESET 0x004
> -#define PCIE_PHY_CMN_REG 0x008
> -#define PCIE_PHY_MAC_RESET 0x00c
> -#define PCIE_PHY_PLL_LOCKED 0x010
> -#define PCIE_PHY_TRSVREG_RESET 0x020
> -#define PCIE_PHY_TRSV_RESET 0x024
> -
> -/* PCIe PHY registers */
> -#define PCIE_PHY_IMPEDANCE 0x004
> -#define PCIE_PHY_PLL_DIV_0 0x008
> -#define PCIE_PHY_PLL_BIAS 0x00c
> -#define PCIE_PHY_DCC_FEEDBACK 0x014
> -#define PCIE_PHY_PLL_DIV_1 0x05c
> -#define PCIE_PHY_COMMON_POWER 0x064
> -#define PCIE_PHY_COMMON_PD_CMN BIT(3)
> -#define PCIE_PHY_TRSV0_EMP_LVL 0x084
> -#define PCIE_PHY_TRSV0_DRV_LVL 0x088
> -#define PCIE_PHY_TRSV0_RXCDR 0x0ac
> -#define PCIE_PHY_TRSV0_POWER 0x0c4
> -#define PCIE_PHY_TRSV0_PD_TSV BIT(7)
> -#define PCIE_PHY_TRSV0_LVCC 0x0dc
> -#define PCIE_PHY_TRSV1_EMP_LVL 0x144
> -#define PCIE_PHY_TRSV1_RXCDR 0x16c
> -#define PCIE_PHY_TRSV1_POWER 0x184
> -#define PCIE_PHY_TRSV1_PD_TSV BIT(7)
> -#define PCIE_PHY_TRSV1_LVCC 0x19c
> -#define PCIE_PHY_TRSV2_EMP_LVL 0x204
> -#define PCIE_PHY_TRSV2_RXCDR 0x22c
> -#define PCIE_PHY_TRSV2_POWER 0x244
> -#define PCIE_PHY_TRSV2_PD_TSV BIT(7)
> -#define PCIE_PHY_TRSV2_LVCC 0x25c
> -#define PCIE_PHY_TRSV3_EMP_LVL 0x2c4
> -#define PCIE_PHY_TRSV3_RXCDR 0x2ec
> -#define PCIE_PHY_TRSV3_POWER 0x304
> -#define PCIE_PHY_TRSV3_PD_TSV BIT(7)
> -#define PCIE_PHY_TRSV3_LVCC 0x31c
> -
> -struct exynos_pcie_phy_data {
> - const struct phy_ops *ops;
> -};
> +#define PCIE_PHY_OFFSET(x) ((x) * 0x4)
> +
> +/* Sysreg FSYS register offsets and bits for Exynos5433 */
> +#define PCIE_EXYNOS5433_PHY_MAC_RESET 0x0208
> +#define PCIE_MAC_RESET_MASK 0xFF
> +#define PCIE_MAC_RESET BIT(4)
> +#define PCIE_EXYNOS5433_PHY_L1SUB_CM_CON 0x1010
> +#define PCIE_REFCLK_GATING_EN BIT(0)
> +#define PCIE_EXYNOS5433_PHY_COMMON_RESET 0x1020
> +#define PCIE_PHY_RESET BIT(0)
> +#define PCIE_EXYNOS5433_PHY_GLOBAL_RESET 0x1040
> +#define PCIE_GLOBAL_RESET BIT(0)
Resets, why is this block not a reset provider?
> +#define PCIE_REFCLK BIT(1)
> +#define PCIE_REFCLK_MASK 0x16
> +#define PCIE_APP_REQ_EXIT_L1_MODE BIT(5)
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v2 4/6] phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433 PCIe PHY
2020-10-26 18:50 ` Rob Herring
@ 2020-10-27 12:28 ` Marek Szyprowski
0 siblings, 0 replies; 20+ messages in thread
From: Marek Szyprowski @ 2020-10-27 12:28 UTC (permalink / raw)
To: Rob Herring
Cc: linux-samsung-soc, PCI, devicetree, linux-kernel@vger.kernel.org,
Jaehoon Chung, Jingoo Han, Krzysztof Kozlowski, Bjorn Helgaas,
Lorenzo Pieralisi, Vinod Koul, Kishon Vijay Abraham I
Hi Rob,
On 26.10.2020 19:50, Rob Herring wrote:
> On Fri, Oct 23, 2020 at 2:58 AM Marek Szyprowski
> <m.szyprowski@samsung.com> wrote:
>> From: Jaehoon Chung <jh80.chung@samsung.com>
>>
>> Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM:
>> dts: exynos: Remove Exynos5440"). Rework this driver to support PCIe PHY
>> variant found in the Exynos5433 SoCs.
>>
>> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
>> [mszyprow: reworked the driver to support only Exynos5433 variant, rebased
>> onto current kernel code, rewrote commit message]
>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
>> ---
>> drivers/phy/samsung/phy-exynos-pcie.c | 304 ++++++++++----------------
>> 1 file changed, 112 insertions(+), 192 deletions(-)
>>
>> diff --git a/drivers/phy/samsung/phy-exynos-pcie.c b/drivers/phy/samsung/phy-exynos-pcie.c
>> index 7e28b1aea0d1..d91de323dd0e 100644
>> --- a/drivers/phy/samsung/phy-exynos-pcie.c
>> +++ b/drivers/phy/samsung/phy-exynos-pcie.c
>> @@ -4,70 +4,41 @@
>> *
>> * Phy provider for PCIe controller on Exynos SoC series
>> *
>> - * Copyright (C) 2017 Samsung Electronics Co., Ltd.
>> + * Copyright (C) 2017-2020 Samsung Electronics Co., Ltd.
>> * Jaehoon Chung <jh80.chung@samsung.com>
>> */
>>
>> -#include <linux/delay.h>
>> #include <linux/io.h>
>> -#include <linux/iopoll.h>
>> -#include <linux/init.h>
>> #include <linux/mfd/syscon.h>
>> -#include <linux/of.h>
>> -#include <linux/of_address.h>
>> #include <linux/of_platform.h>
>> #include <linux/platform_device.h>
>> #include <linux/phy/phy.h>
>> #include <linux/regmap.h>
>>
>> -/* PCIe Purple registers */
>> -#define PCIE_PHY_GLOBAL_RESET 0x000
>> -#define PCIE_PHY_COMMON_RESET 0x004
>> -#define PCIE_PHY_CMN_REG 0x008
>> -#define PCIE_PHY_MAC_RESET 0x00c
>> -#define PCIE_PHY_PLL_LOCKED 0x010
>> -#define PCIE_PHY_TRSVREG_RESET 0x020
>> -#define PCIE_PHY_TRSV_RESET 0x024
>> -
>> -/* PCIe PHY registers */
>> -#define PCIE_PHY_IMPEDANCE 0x004
>> -#define PCIE_PHY_PLL_DIV_0 0x008
>> -#define PCIE_PHY_PLL_BIAS 0x00c
>> -#define PCIE_PHY_DCC_FEEDBACK 0x014
>> -#define PCIE_PHY_PLL_DIV_1 0x05c
>> -#define PCIE_PHY_COMMON_POWER 0x064
>> -#define PCIE_PHY_COMMON_PD_CMN BIT(3)
>> -#define PCIE_PHY_TRSV0_EMP_LVL 0x084
>> -#define PCIE_PHY_TRSV0_DRV_LVL 0x088
>> -#define PCIE_PHY_TRSV0_RXCDR 0x0ac
>> -#define PCIE_PHY_TRSV0_POWER 0x0c4
>> -#define PCIE_PHY_TRSV0_PD_TSV BIT(7)
>> -#define PCIE_PHY_TRSV0_LVCC 0x0dc
>> -#define PCIE_PHY_TRSV1_EMP_LVL 0x144
>> -#define PCIE_PHY_TRSV1_RXCDR 0x16c
>> -#define PCIE_PHY_TRSV1_POWER 0x184
>> -#define PCIE_PHY_TRSV1_PD_TSV BIT(7)
>> -#define PCIE_PHY_TRSV1_LVCC 0x19c
>> -#define PCIE_PHY_TRSV2_EMP_LVL 0x204
>> -#define PCIE_PHY_TRSV2_RXCDR 0x22c
>> -#define PCIE_PHY_TRSV2_POWER 0x244
>> -#define PCIE_PHY_TRSV2_PD_TSV BIT(7)
>> -#define PCIE_PHY_TRSV2_LVCC 0x25c
>> -#define PCIE_PHY_TRSV3_EMP_LVL 0x2c4
>> -#define PCIE_PHY_TRSV3_RXCDR 0x2ec
>> -#define PCIE_PHY_TRSV3_POWER 0x304
>> -#define PCIE_PHY_TRSV3_PD_TSV BIT(7)
>> -#define PCIE_PHY_TRSV3_LVCC 0x31c
>> -
>> -struct exynos_pcie_phy_data {
>> - const struct phy_ops *ops;
>> -};
>> +#define PCIE_PHY_OFFSET(x) ((x) * 0x4)
>> +
>> +/* Sysreg FSYS register offsets and bits for Exynos5433 */
>> +#define PCIE_EXYNOS5433_PHY_MAC_RESET 0x0208
>> +#define PCIE_MAC_RESET_MASK 0xFF
>> +#define PCIE_MAC_RESET BIT(4)
>> +#define PCIE_EXYNOS5433_PHY_L1SUB_CM_CON 0x1010
>> +#define PCIE_REFCLK_GATING_EN BIT(0)
>> +#define PCIE_EXYNOS5433_PHY_COMMON_RESET 0x1020
>> +#define PCIE_PHY_RESET BIT(0)
>> +#define PCIE_EXYNOS5433_PHY_GLOBAL_RESET 0x1040
>> +#define PCIE_GLOBAL_RESET BIT(0)
> Resets, why is this block not a reset provider?
Because most of those registers need to be configured together with the
rest of the PHY registers. IMHO there is no simple "do the reset" logic
there. There is also PHY reference clock configuration there. This phy
driver is already Exynos5433 specific and I see no point in extracting
separate reset driver from it. Other Exynos PHY drivers also access PMU
and SYSREG via the respective regmaps and don't use any kind of reset
drivers.
>> +#define PCIE_REFCLK BIT(1)
>> +#define PCIE_REFCLK_MASK 0x16
>> +#define PCIE_APP_REQ_EXIT_L1_MODE BIT(5)
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 5/6] pci: dwc: pci-exynos: rework the driver to support Exynos5433 variant
2020-10-23 7:57 ` [PATCH v2 0/6] Add DW PCIe support for Exynos5433 SoCs Marek Szyprowski
` (3 preceding siblings ...)
2020-10-23 7:57 ` [PATCH v2 4/6] phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433 PCIe PHY Marek Szyprowski
@ 2020-10-23 7:57 ` Marek Szyprowski
2020-10-23 15:09 ` kernel test robot
` (2 more replies)
2020-10-23 7:57 ` [PATCH v2 6/6] arm64: dts: exynos: add the WiFi/PCIe support to TM2(e) boards Marek Szyprowski
5 siblings, 3 replies; 20+ messages in thread
From: Marek Szyprowski @ 2020-10-23 7:57 UTC (permalink / raw)
To: linux-samsung-soc, linux-pci
Cc: devicetree, linux-kernel, Jaehoon Chung, Marek Szyprowski,
Jingoo Han, Krzysztof Kozlowski, Bjorn Helgaas, Lorenzo Pieralisi,
Vinod Koul, Kishon Vijay Abraham I, Rob Herring
From: Jaehoon Chung <jh80.chung@samsung.com>
Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM:
dts: exynos: Remove Exynos5440"). Rework this driver to support DWC PCIe
variant found in the Exynos5433 SoCs.
The main difference in Exynos5433 variant is lack of the MSI support
(the MSI interrupt is not even routed to the CPU).
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
[mszyprow: reworked the driver to support only Exynos5433 variant,
simplified code, rebased onto current kernel code, added
regulator support, converted to the regular platform driver,
removed MSI related code, rewrote commit message]
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
---
drivers/pci/controller/dwc/Kconfig | 3 +-
drivers/pci/controller/dwc/pci-exynos.c | 358 ++++++++++--------------
drivers/pci/quirks.c | 1 +
3 files changed, 145 insertions(+), 217 deletions(-)
diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
index bc049865f8e0..ade07abd23c9 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -84,8 +84,7 @@ config PCIE_DW_PLAT_EP
config PCI_EXYNOS
bool "Samsung Exynos PCIe controller"
- depends on SOC_EXYNOS5440 || COMPILE_TEST
- depends on PCI_MSI_IRQ_DOMAIN
+ depends on ARCH_EXYNOS || COMPILE_TEST
select PCIE_DW_HOST
config PCI_IMX6
diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controller/dwc/pci-exynos.c
index 242683cde04a..58056fbdc2fa 100644
--- a/drivers/pci/controller/dwc/pci-exynos.c
+++ b/drivers/pci/controller/dwc/pci-exynos.c
@@ -2,26 +2,23 @@
/*
* PCIe host controller driver for Samsung Exynos SoCs
*
- * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Copyright (C) 2013-2020 Samsung Electronics Co., Ltd.
* https://www.samsung.com
*
* Author: Jingoo Han <jg1.han@samsung.com>
+ * Jaehoon Chung <jh80.chung@samsung.com>
*/
#include <linux/clk.h>
#include <linux/delay.h>
-#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/of_device.h>
-#include <linux/of_gpio.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/phy/phy.h>
-#include <linux/resource.h>
-#include <linux/signal.h>
-#include <linux/types.h>
+#include <linux/regulator/consumer.h>
#include "pcie-designware.h"
@@ -37,102 +34,47 @@
#define PCIE_IRQ_SPECIAL 0x008
#define PCIE_IRQ_EN_PULSE 0x00c
#define PCIE_IRQ_EN_LEVEL 0x010
-#define IRQ_MSI_ENABLE BIT(2)
#define PCIE_IRQ_EN_SPECIAL 0x014
-#define PCIE_PWR_RESET 0x018
+#define PCIE_SW_WAKE 0x018
+#define PCIE_BUS_EN BIT(1)
#define PCIE_CORE_RESET 0x01c
#define PCIE_CORE_RESET_ENABLE BIT(0)
#define PCIE_STICKY_RESET 0x020
#define PCIE_NONSTICKY_RESET 0x024
#define PCIE_APP_INIT_RESET 0x028
#define PCIE_APP_LTSSM_ENABLE 0x02c
-#define PCIE_ELBI_RDLH_LINKUP 0x064
+#define PCIE_ELBI_RDLH_LINKUP 0x074
+#define PCIE_ELBI_XMLH_LINKUP BIT(4)
#define PCIE_ELBI_LTSSM_ENABLE 0x1
#define PCIE_ELBI_SLV_AWMISC 0x11c
#define PCIE_ELBI_SLV_ARMISC 0x120
#define PCIE_ELBI_SLV_DBI_ENABLE BIT(21)
-struct exynos_pcie_mem_res {
- void __iomem *elbi_base; /* DT 0th resource: PCIe CTRL */
-};
-
-struct exynos_pcie_clk_res {
- struct clk *clk;
- struct clk *bus_clk;
-};
+/* DBI register */
+#define PCIE_MISC_CONTROL_1_OFF 0x8BC
+#define DBI_RO_WR_EN BIT(0)
struct exynos_pcie {
- struct dw_pcie *pci;
- struct exynos_pcie_mem_res *mem_res;
- struct exynos_pcie_clk_res *clk_res;
- const struct exynos_pcie_ops *ops;
- int reset_gpio;
-
+ struct dw_pcie pci;
+ void __iomem *elbi_base;
+ struct clk *clk;
+ struct clk *bus_clk;
struct phy *phy;
+ struct regulator_bulk_data supplies[2];
};
-struct exynos_pcie_ops {
- int (*get_mem_resources)(struct platform_device *pdev,
- struct exynos_pcie *ep);
- int (*get_clk_resources)(struct exynos_pcie *ep);
- int (*init_clk_resources)(struct exynos_pcie *ep);
- void (*deinit_clk_resources)(struct exynos_pcie *ep);
-};
-
-static int exynos5440_pcie_get_mem_resources(struct platform_device *pdev,
- struct exynos_pcie *ep)
-{
- struct dw_pcie *pci = ep->pci;
- struct device *dev = pci->dev;
-
- ep->mem_res = devm_kzalloc(dev, sizeof(*ep->mem_res), GFP_KERNEL);
- if (!ep->mem_res)
- return -ENOMEM;
-
- ep->mem_res->elbi_base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(ep->mem_res->elbi_base))
- return PTR_ERR(ep->mem_res->elbi_base);
-
- return 0;
-}
-
-static int exynos5440_pcie_get_clk_resources(struct exynos_pcie *ep)
-{
- struct dw_pcie *pci = ep->pci;
- struct device *dev = pci->dev;
-
- ep->clk_res = devm_kzalloc(dev, sizeof(*ep->clk_res), GFP_KERNEL);
- if (!ep->clk_res)
- return -ENOMEM;
-
- ep->clk_res->clk = devm_clk_get(dev, "pcie");
- if (IS_ERR(ep->clk_res->clk)) {
- dev_err(dev, "Failed to get pcie rc clock\n");
- return PTR_ERR(ep->clk_res->clk);
- }
-
- ep->clk_res->bus_clk = devm_clk_get(dev, "pcie_bus");
- if (IS_ERR(ep->clk_res->bus_clk)) {
- dev_err(dev, "Failed to get pcie bus clock\n");
- return PTR_ERR(ep->clk_res->bus_clk);
- }
-
- return 0;
-}
-
-static int exynos5440_pcie_init_clk_resources(struct exynos_pcie *ep)
+static int exynos_pcie_init_clk_resources(struct exynos_pcie *ep)
{
- struct dw_pcie *pci = ep->pci;
- struct device *dev = pci->dev;
+ struct device *dev = ep->pci.dev;
int ret;
- ret = clk_prepare_enable(ep->clk_res->clk);
+ ret = clk_prepare_enable(ep->clk);
if (ret) {
dev_err(dev, "cannot enable pcie rc clock");
return ret;
}
- ret = clk_prepare_enable(ep->clk_res->bus_clk);
+ ret = clk_prepare_enable(ep->bus_clk);
if (ret) {
dev_err(dev, "cannot enable pcie bus clock");
goto err_bus_clk;
@@ -141,24 +83,17 @@ static int exynos5440_pcie_init_clk_resources(struct exynos_pcie *ep)
return 0;
err_bus_clk:
- clk_disable_unprepare(ep->clk_res->clk);
+ clk_disable_unprepare(ep->clk);
return ret;
}
-static void exynos5440_pcie_deinit_clk_resources(struct exynos_pcie *ep)
+static void exynos_pcie_deinit_clk_resources(struct exynos_pcie *ep)
{
- clk_disable_unprepare(ep->clk_res->bus_clk);
- clk_disable_unprepare(ep->clk_res->clk);
+ clk_disable_unprepare(ep->bus_clk);
+ clk_disable_unprepare(ep->clk);
}
-static const struct exynos_pcie_ops exynos5440_pcie_ops = {
- .get_mem_resources = exynos5440_pcie_get_mem_resources,
- .get_clk_resources = exynos5440_pcie_get_clk_resources,
- .init_clk_resources = exynos5440_pcie_init_clk_resources,
- .deinit_clk_resources = exynos5440_pcie_deinit_clk_resources,
-};
-
static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg)
{
writel(val, base + reg);
@@ -173,67 +108,57 @@ static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *ep, bool on)
{
u32 val;
- val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_ELBI_SLV_AWMISC);
+ val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_AWMISC);
if (on)
val |= PCIE_ELBI_SLV_DBI_ENABLE;
else
val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
- exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_ELBI_SLV_AWMISC);
+ exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_AWMISC);
}
static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *ep, bool on)
{
u32 val;
- val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_ELBI_SLV_ARMISC);
+ val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_ARMISC);
if (on)
val |= PCIE_ELBI_SLV_DBI_ENABLE;
else
val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
- exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_ELBI_SLV_ARMISC);
+ exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_ARMISC);
}
static void exynos_pcie_assert_core_reset(struct exynos_pcie *ep)
{
u32 val;
- val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_CORE_RESET);
+ val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET);
val &= ~PCIE_CORE_RESET_ENABLE;
- exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_CORE_RESET);
- exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_PWR_RESET);
- exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_STICKY_RESET);
- exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_NONSTICKY_RESET);
+ exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET);
+ exynos_pcie_writel(ep->elbi_base, 0, PCIE_STICKY_RESET);
+ exynos_pcie_writel(ep->elbi_base, 0, PCIE_NONSTICKY_RESET);
}
static void exynos_pcie_deassert_core_reset(struct exynos_pcie *ep)
{
u32 val;
- val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_CORE_RESET);
+ val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET);
val |= PCIE_CORE_RESET_ENABLE;
- exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_CORE_RESET);
- exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_STICKY_RESET);
- exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_NONSTICKY_RESET);
- exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_APP_INIT_RESET);
- exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_APP_INIT_RESET);
-}
-
-static void exynos_pcie_assert_reset(struct exynos_pcie *ep)
-{
- struct dw_pcie *pci = ep->pci;
- struct device *dev = pci->dev;
-
- if (ep->reset_gpio >= 0)
- devm_gpio_request_one(dev, ep->reset_gpio,
- GPIOF_OUT_INIT_HIGH, "RESET");
+ exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET);
+ exynos_pcie_writel(ep->elbi_base, 1, PCIE_STICKY_RESET);
+ exynos_pcie_writel(ep->elbi_base, 1, PCIE_NONSTICKY_RESET);
+ exynos_pcie_writel(ep->elbi_base, 1, PCIE_APP_INIT_RESET);
+ exynos_pcie_writel(ep->elbi_base, 0, PCIE_APP_INIT_RESET);
}
static int exynos_pcie_establish_link(struct exynos_pcie *ep)
{
- struct dw_pcie *pci = ep->pci;
+ struct dw_pcie *pci = &ep->pci;
struct pcie_port *pp = &pci->pp;
struct device *dev = pci->dev;
+ u32 val;
if (dw_pcie_link_up(pci)) {
dev_err(dev, "Link already up\n");
@@ -243,19 +168,25 @@ static int exynos_pcie_establish_link(struct exynos_pcie *ep)
exynos_pcie_assert_core_reset(ep);
phy_reset(ep->phy);
-
- exynos_pcie_writel(ep->mem_res->elbi_base, 1,
- PCIE_PWR_RESET);
-
phy_power_on(ep->phy);
phy_init(ep->phy);
exynos_pcie_deassert_core_reset(ep);
+
+ val = exynos_pcie_readl(ep->elbi_base, PCIE_SW_WAKE);
+ val &= ~PCIE_BUS_EN;
+ exynos_pcie_writel(ep->elbi_base, val, PCIE_SW_WAKE);
+
+ /*
+ * Enable DBI_RO_WR_EN bit.
+ * - When set to 1, some RO and HWinit bits are wriatble from
+ * the local application through the DBI.
+ */
+ dw_pcie_writel_dbi(pci, PCIE_MISC_CONTROL_1_OFF, DBI_RO_WR_EN);
dw_pcie_setup_rc(pp);
- exynos_pcie_assert_reset(ep);
/* assert LTSSM enable */
- exynos_pcie_writel(ep->mem_res->elbi_base, PCIE_ELBI_LTSSM_ENABLE,
+ exynos_pcie_writel(ep->elbi_base, PCIE_ELBI_LTSSM_ENABLE,
PCIE_APP_LTSSM_ENABLE);
/* check if the link is up or not */
@@ -270,18 +201,8 @@ static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *ep)
{
u32 val;
- val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_IRQ_PULSE);
- exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_PULSE);
-}
-
-static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep)
-{
- u32 val;
-
- /* enable INTX interrupt */
- val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
- IRQ_INTC_ASSERT | IRQ_INTD_ASSERT;
- exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_EN_PULSE);
+ val = exynos_pcie_readl(ep->elbi_base, PCIE_IRQ_PULSE);
+ exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_PULSE);
}
static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)
@@ -292,26 +213,14 @@ static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)
return IRQ_HANDLED;
}
-static void exynos_pcie_msi_init(struct exynos_pcie *ep)
-{
- struct dw_pcie *pci = ep->pci;
- struct pcie_port *pp = &pci->pp;
- u32 val;
-
- dw_pcie_msi_init(pp);
-
- /* enable MSI interrupt */
- val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_IRQ_EN_LEVEL);
- val |= IRQ_MSI_ENABLE;
- exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_EN_LEVEL);
-}
-
-static void exynos_pcie_enable_interrupts(struct exynos_pcie *ep)
+static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep)
{
- exynos_pcie_enable_irq_pulse(ep);
+ u32 val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
+ IRQ_INTC_ASSERT | IRQ_INTD_ASSERT;
- if (IS_ENABLED(CONFIG_PCI_MSI))
- exynos_pcie_msi_init(ep);
+ exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_EN_PULSE);
+ exynos_pcie_writel(ep->elbi_base, 0, PCIE_IRQ_EN_LEVEL);
+ exynos_pcie_writel(ep->elbi_base, 0, PCIE_IRQ_EN_SPECIAL);
}
static u32 exynos_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
@@ -372,11 +281,8 @@ static int exynos_pcie_link_up(struct dw_pcie *pci)
struct exynos_pcie *ep = to_exynos_pcie(pci);
u32 val;
- val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_ELBI_RDLH_LINKUP);
- if (val == PCIE_ELBI_LTSSM_ENABLE)
- return 1;
-
- return 0;
+ val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_RDLH_LINKUP);
+ return (val & PCIE_ELBI_XMLH_LINKUP);
}
static int exynos_pcie_host_init(struct pcie_port *pp)
@@ -386,10 +292,8 @@ static int exynos_pcie_host_init(struct pcie_port *pp)
pp->bridge->ops = &exynos_pci_ops;
- exynos_pcie_establish_link(ep);
- exynos_pcie_enable_interrupts(ep);
-
- return 0;
+ exynos_pcie_enable_irq_pulse(ep);
+ return exynos_pcie_establish_link(ep);
}
static const struct dw_pcie_host_ops exynos_pcie_host_ops = {
@@ -399,28 +303,22 @@ static const struct dw_pcie_host_ops exynos_pcie_host_ops = {
static int __init exynos_add_pcie_port(struct exynos_pcie *ep,
struct platform_device *pdev)
{
- struct dw_pcie *pci = ep->pci;
+ struct dw_pcie *pci = &ep->pci;
struct pcie_port *pp = &pci->pp;
struct device *dev = &pdev->dev;
int ret;
- pp->irq = platform_get_irq(pdev, 1);
+ pp->irq = platform_get_irq(pdev, 0);
if (pp->irq < 0)
return pp->irq;
ret = devm_request_irq(dev, pp->irq, exynos_pcie_irq_handler,
- IRQF_SHARED, "exynos-pcie", ep);
+ IRQF_SHARED, "exynos-pcie", ep);
if (ret) {
dev_err(dev, "failed to request irq\n");
return ret;
}
- if (IS_ENABLED(CONFIG_PCI_MSI)) {
- pp->msi_irq = platform_get_irq(pdev, 0);
- if (pp->msi_irq < 0)
- return pp->msi_irq;
- }
-
pp->ops = &exynos_pcie_host_ops;
ret = dw_pcie_host_init(pp);
@@ -438,10 +336,9 @@ static const struct dw_pcie_ops dw_pcie_ops = {
.link_up = exynos_pcie_link_up,
};
-static int __init exynos_pcie_probe(struct platform_device *pdev)
+static int exynos_pcie_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
- struct dw_pcie *pci;
struct exynos_pcie *ep;
struct device_node *np = dev->of_node;
int ret;
@@ -450,42 +347,49 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
if (!ep)
return -ENOMEM;
- pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
- if (!pci)
- return -ENOMEM;
-
- pci->dev = dev;
- pci->ops = &dw_pcie_ops;
+ ep->pci.dev = dev;
+ ep->pci.ops = &dw_pcie_ops;
- ep->pci = pci;
- ep->ops = (const struct exynos_pcie_ops *)
- of_device_get_match_data(dev);
+ ep->phy = devm_of_phy_get(dev, np, NULL);
+ if (IS_ERR(ep->phy))
+ return PTR_ERR(ep->phy);
- ep->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
+ /* External Local Bus interface (ELBI) registers */
+ ep->elbi_base = devm_platform_ioremap_resource_byname(pdev, "elbi");
+ if (IS_ERR(ep->elbi_base))
+ return PTR_ERR(ep->elbi_base);
- ep->phy = devm_of_phy_get(dev, np, NULL);
- if (IS_ERR(ep->phy)) {
- if (PTR_ERR(ep->phy) != -ENODEV)
- return PTR_ERR(ep->phy);
+ /* Data Bus Interface (DBI) registers */
+ ep->pci.dbi_base = devm_platform_ioremap_resource_byname(pdev, "dbi");
+ if (IS_ERR(ep->pci.dbi_base))
+ return PTR_ERR(ep->pci.dbi_base);
- ep->phy = NULL;
+ ep->clk = devm_clk_get(dev, "pcie");
+ if (IS_ERR(ep->clk)) {
+ dev_err(dev, "Failed to get pcie rc clock\n");
+ return PTR_ERR(ep->clk);
}
- if (ep->ops && ep->ops->get_mem_resources) {
- ret = ep->ops->get_mem_resources(pdev, ep);
- if (ret)
- return ret;
+ ep->bus_clk = devm_clk_get(dev, "pcie_bus");
+ if (IS_ERR(ep->bus_clk)) {
+ dev_err(dev, "Failed to get pcie bus clock\n");
+ return PTR_ERR(ep->bus_clk);
}
- if (ep->ops && ep->ops->get_clk_resources &&
- ep->ops->init_clk_resources) {
- ret = ep->ops->get_clk_resources(ep);
- if (ret)
- return ret;
- ret = ep->ops->init_clk_resources(ep);
- if (ret)
- return ret;
- }
+ ep->supplies[0].supply = "vdd18";
+ ep->supplies[1].supply = "vdd10";
+ ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ep->supplies),
+ ep->supplies);
+ if (ret)
+ return ret;
+
+ ret = exynos_pcie_init_clk_resources(ep);
+ if (ret)
+ return ret;
+
+ ret = regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep->supplies);
+ if (ret)
+ return ret;
platform_set_drvdata(pdev, ep);
@@ -497,9 +401,9 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
fail_probe:
phy_exit(ep->phy);
+ exynos_pcie_deinit_clk_resources(ep);
+ regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies);
- if (ep->ops && ep->ops->deinit_clk_resources)
- ep->ops->deinit_clk_resources(ep);
return ret;
}
@@ -507,32 +411,56 @@ static int __exit exynos_pcie_remove(struct platform_device *pdev)
{
struct exynos_pcie *ep = platform_get_drvdata(pdev);
- if (ep->ops && ep->ops->deinit_clk_resources)
- ep->ops->deinit_clk_resources(ep);
+ phy_power_off(ep->phy);
+ phy_exit(ep->phy);
+ exynos_pcie_deinit_clk_resources(ep);
+ regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies);
return 0;
}
+static int __maybe_unused exynos_pcie_suspend_noirq(struct device *dev)
+{
+ struct exynos_pcie *ep = dev_get_drvdata(dev);
+
+ phy_power_off(ep->phy);
+ phy_exit(ep->phy);
+ regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies);
+
+ return 0;
+}
+
+static int __maybe_unused exynos_pcie_resume_noirq(struct device *dev)
+{
+ struct exynos_pcie *ep = dev_get_drvdata(dev);
+ struct dw_pcie *pci = &ep->pci;
+ struct pcie_port *pp = &pci->pp;
+ int ret;
+
+ ret = regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep->supplies);
+ if (ret)
+ return ret;
+ /* exynos_pcie_host_init controls ep->phy */
+ return exynos_pcie_host_init(pp);
+}
+
+static const struct dev_pm_ops exynos_pcie_pm_ops = {
+ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(exynos_pcie_suspend_noirq,
+ exynos_pcie_resume_noirq)
+};
+
static const struct of_device_id exynos_pcie_of_match[] = {
- {
- .compatible = "samsung,exynos5440-pcie",
- .data = &exynos5440_pcie_ops
- },
- {},
+ { .compatible = "samsung,exynos5433-pcie", },
+ { },
};
static struct platform_driver exynos_pcie_driver = {
+ .probe = exynos_pcie_probe,
.remove = __exit_p(exynos_pcie_remove),
.driver = {
.name = "exynos-pcie",
.of_match_table = exynos_pcie_of_match,
+ .pm = &exynos_pcie_pm_ops,
},
};
-
-/* Exynos PCIe driver does not allow module unload */
-
-static int __init exynos_pcie_init(void)
-{
- return platform_driver_probe(&exynos_pcie_driver, exynos_pcie_probe);
-}
-subsys_initcall(exynos_pcie_init);
+builtin_platform_driver(exynos_pcie_driver);
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index f70692ac79c5..8b93f0bba1f2 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2522,6 +2522,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disab
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG, 0xa5e3, quirk_disable_all_msi);
/* Disable MSI on chipsets that are known to not support it */
static void quirk_disable_msi(struct pci_dev *dev)
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v2 5/6] pci: dwc: pci-exynos: rework the driver to support Exynos5433 variant
2020-10-23 7:57 ` [PATCH v2 5/6] pci: dwc: pci-exynos: rework the driver to support Exynos5433 variant Marek Szyprowski
@ 2020-10-23 15:09 ` kernel test robot
2020-10-24 3:12 ` Jingoo Han
2020-10-26 19:14 ` Rob Herring
2 siblings, 0 replies; 20+ messages in thread
From: kernel test robot @ 2020-10-23 15:09 UTC (permalink / raw)
To: Marek Szyprowski, linux-samsung-soc, linux-pci
Cc: kbuild-all, clang-built-linux, devicetree, linux-kernel,
Jaehoon Chung, Marek Szyprowski, Jingoo Han, Krzysztof Kozlowski,
Bjorn Helgaas, Lorenzo Pieralisi
[-- Attachment #1: Type: text/plain, Size: 2186 bytes --]
Hi Marek,
I love your patch! Perhaps something to improve:
[auto build test WARNING on pci/next]
[also build test WARNING on linus/master next-20201023]
[cannot apply to robh/for-next linux/master v5.9]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Marek-Szyprowski/Add-DW-PCIe-support-for-Exynos5433-SoCs/20201023-155914
base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
config: x86_64-randconfig-a015-20201023 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project 147b9497e79a98a8614b2b5eb4ba653b44f6b6f0)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install x86_64 cross compiling tool for clang build
# apt-get install binutils-x86-64-linux-gnu
# https://github.com/0day-ci/linux/commit/2935808380d3908b7fc99713723b4446e141868b
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Marek-Szyprowski/Add-DW-PCIe-support-for-Exynos5433-SoCs/20201023-155914
git checkout 2935808380d3908b7fc99713723b4446e141868b
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>, old ones prefixed by <<):
>> WARNING: modpost: vmlinux.o(.text+0xd0c889): Section mismatch in reference from the function exynos_pcie_probe() to the function .init.text:exynos_add_pcie_port()
The function exynos_pcie_probe() references
the function __init exynos_add_pcie_port().
This is often because exynos_pcie_probe lacks a __init
annotation or the annotation of exynos_add_pcie_port is wrong.
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 39195 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v2 5/6] pci: dwc: pci-exynos: rework the driver to support Exynos5433 variant
2020-10-23 7:57 ` [PATCH v2 5/6] pci: dwc: pci-exynos: rework the driver to support Exynos5433 variant Marek Szyprowski
2020-10-23 15:09 ` kernel test robot
@ 2020-10-24 3:12 ` Jingoo Han
2020-10-26 2:49 ` Jaehoon Chung
2020-10-26 19:14 ` Rob Herring
2 siblings, 1 reply; 20+ messages in thread
From: Jingoo Han @ 2020-10-24 3:12 UTC (permalink / raw)
To: Marek Szyprowski, linux-samsung-soc@vger.kernel.org,
linux-pci@vger.kernel.org
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Jaehoon Chung, Krzysztof Kozlowski, Bjorn Helgaas,
Lorenzo Pieralisi, Vinod Koul, Kishon Vijay Abraham I,
Rob Herring, Han Jingoo
On 10/23/20, 3:58 AM, Marek Szyprowski wrote:
>
> From: Jaehoon Chung <jh80.chung@samsung.com>
>
> Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM:
> dts: exynos: Remove Exynos5440"). Rework this driver to support DWC PCIe
> variant found in the Exynos5433 SoCs.
>
> The main difference in Exynos5433 variant is lack of the MSI support
> (the MSI interrupt is not even routed to the CPU).
>
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
> [mszyprow: reworked the driver to support only Exynos5433 variant,
> simplified code, rebased onto current kernel code, added
> regulator support, converted to the regular platform driver,
> removed MSI related code, rewrote commit message]
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
> drivers/pci/controller/dwc/Kconfig | 3 +-
> drivers/pci/controller/dwc/pci-exynos.c | 358 ++++++++++--------------
> drivers/pci/quirks.c | 1 +
> 3 files changed, 145 insertions(+), 217 deletions(-)
[....]
> diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controller/dwc/pci-exynos.c
> index 242683cde04a..58056fbdc2fa 100644
> --- a/drivers/pci/controller/dwc/pci-exynos.c
> +++ b/drivers/pci/controller/dwc/pci-exynos.c
> @@ -2,26 +2,23 @@
> /*
> * PCIe host controller driver for Samsung Exynos SoCs
> *
> - * Copyright (C) 2013 Samsung Electronics Co., Ltd.
> + * Copyright (C) 2013-2020 Samsung Electronics Co., Ltd.
> * https://www.samsung.com
> *
> * Author: Jingoo Han <jg1.han@samsung.com>
> + * Jaehoon Chung <jh80.chung@samsung.com>
Would you explain the reason why you add him as an author?
If reasonable, I will accept it. Also, I want gentle discussion, not aggressive one.
Thank you.
Best regards,
Jingoo Han
> */
[....]
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v2 5/6] pci: dwc: pci-exynos: rework the driver to support Exynos5433 variant
2020-10-24 3:12 ` Jingoo Han
@ 2020-10-26 2:49 ` Jaehoon Chung
2020-10-26 4:08 ` Jingoo Han
0 siblings, 1 reply; 20+ messages in thread
From: Jaehoon Chung @ 2020-10-26 2:49 UTC (permalink / raw)
To: Jingoo Han, Marek Szyprowski, linux-samsung-soc@vger.kernel.org,
linux-pci@vger.kernel.org
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Krzysztof Kozlowski, Bjorn Helgaas, Lorenzo Pieralisi, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring
Dear Jingoo,
On 10/24/20 12:12 PM, Jingoo Han wrote:
> On 10/23/20, 3:58 AM, Marek Szyprowski wrote:
>>
>> From: Jaehoon Chung <jh80.chung@samsung.com>
>>
>> Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM:
>> dts: exynos: Remove Exynos5440"). Rework this driver to support DWC PCIe
>> variant found in the Exynos5433 SoCs.
>>
>> The main difference in Exynos5433 variant is lack of the MSI support
>> (the MSI interrupt is not even routed to the CPU).
>>
>> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
>> [mszyprow: reworked the driver to support only Exynos5433 variant,
>> simplified code, rebased onto current kernel code, added
>> regulator support, converted to the regular platform driver,
>> removed MSI related code, rewrote commit message]
>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
>> ---
>> drivers/pci/controller/dwc/Kconfig | 3 +-
>> drivers/pci/controller/dwc/pci-exynos.c | 358 ++++++++++--------------
>> drivers/pci/quirks.c | 1 +
>> 3 files changed, 145 insertions(+), 217 deletions(-)
>
> [....]
>
>> diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controller/dwc/pci-exynos.c
>> index 242683cde04a..58056fbdc2fa 100644
>> --- a/drivers/pci/controller/dwc/pci-exynos.c
>> +++ b/drivers/pci/controller/dwc/pci-exynos.c
>> @@ -2,26 +2,23 @@
>> /*
>> * PCIe host controller driver for Samsung Exynos SoCs
>> *
>> - * Copyright (C) 2013 Samsung Electronics Co., Ltd.
>> + * Copyright (C) 2013-2020 Samsung Electronics Co., Ltd.
>> * https://www.samsung.com
>> *
>> * Author: Jingoo Han <jg1.han@samsung.com>
>> + * Jaehoon Chung <jh80.chung@samsung.com>
>
> Would you explain the reason why you add him as an author?
> If reasonable, I will accept it. Also, I want gentle discussion, not aggressive one.
> Thank you.
It's not important to add me as author. :)
If you don't want to accept it, i think it can be removed it.
I think that pci-exynos was supported on only exynos5440.
As you know, exynos5440 was not common as compared with other exynos SoC.
After this patch, pci-exynos is re-newed.
Best Regards,
Jaehoon Chung
>
> Best regards,
> Jingoo Han
>
>> */
>
> [....]
>
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v2 5/6] pci: dwc: pci-exynos: rework the driver to support Exynos5433 variant
2020-10-26 2:49 ` Jaehoon Chung
@ 2020-10-26 4:08 ` Jingoo Han
0 siblings, 0 replies; 20+ messages in thread
From: Jingoo Han @ 2020-10-26 4:08 UTC (permalink / raw)
To: Jaehoon Chung, Marek Szyprowski,
linux-samsung-soc@vger.kernel.org, linux-pci@vger.kernel.org
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Krzysztof Kozlowski, Bjorn Helgaas, Lorenzo Pieralisi, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Han Jingoo
On 10/25/20, 10:49 PM, Jaehoon Chung wrote:
>
> Dear Jingoo,
Hi Jaehoon,
> On 10/24/20 12:12 PM, Jingoo Han wrote:
> > On 10/23/20, 3:58 AM, Marek Szyprowski wrote:
> >>
> >> From: Jaehoon Chung <jh80.chung@samsung.com>
> >>
> >> Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM:
> >> dts: exynos: Remove Exynos5440"). Rework this driver to support DWC PCIe
> >> variant found in the Exynos5433 SoCs.
> >>
> >> The main difference in Exynos5433 variant is lack of the MSI support
> >> (the MSI interrupt is not even routed to the CPU).
> >>
> >> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
> >> [mszyprow: reworked the driver to support only Exynos5433 variant,
> >> simplified code, rebased onto current kernel code, added
> >> regulator support, converted to the regular platform driver,
> >> removed MSI related code, rewrote commit message]
> >> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> >> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
> >> ---
> >> drivers/pci/controller/dwc/Kconfig | 3 +-
> >> drivers/pci/controller/dwc/pci-exynos.c | 358 ++++++++++--------------
> >> drivers/pci/quirks.c | 1 +
> >> 3 files changed, 145 insertions(+), 217 deletions(-)
> >
> > [....]
> >
> >> diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controller/dwc/pci-exynos.c
> >> index 242683cde04a..58056fbdc2fa 100644
> >> --- a/drivers/pci/controller/dwc/pci-exynos.c
> >> +++ b/drivers/pci/controller/dwc/pci-exynos.c
> >> @@ -2,26 +2,23 @@
> >> /*
> >> * PCIe host controller driver for Samsung Exynos SoCs
> >> *
> >> - * Copyright (C) 2013 Samsung Electronics Co., Ltd.
> >> + * Copyright (C) 2013-2020 Samsung Electronics Co., Ltd.
> >> * https://www.samsung.com
> >> *
> >> * Author: Jingoo Han <jg1.han@samsung.com>
> >> + * Jaehoon Chung <jh80.chung@samsung.com>
> >
> > Would you explain the reason why you add him as an author?
> > If reasonable, I will accept it. Also, I want gentle discussion, not aggressive one.
> > Thank you.
>
> It's not important to add me as author. :)
> If you don't want to accept it, i think it can be removed it.
> I think that pci-exynos was supported on only exynos5440.
> As you know, exynos5440 was not common as compared with other exynos SoC.
> After this patch, pci-exynos is re-newed.
Ah, I just thought that you are not interested in Exynos PCIe anymore. However, if you want
to submit other patches for supporting other Exynos PCIe, adding you as an author is ok.
There are many Exynos SoCs that support PCIe IP. So, if someone like you who have good
experience on Exynos, helps submitting patches for Exynos PCIe, it would be very helpful. :-)
Thank you.
Best regards,
Jingoo Han
>
> Best Regards,
> Jaehoon Chung
>
> >
> > Best regards,
> > Jingoo Han
> >
> >> */
> >
> > [....]
> >
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 5/6] pci: dwc: pci-exynos: rework the driver to support Exynos5433 variant
2020-10-23 7:57 ` [PATCH v2 5/6] pci: dwc: pci-exynos: rework the driver to support Exynos5433 variant Marek Szyprowski
2020-10-23 15:09 ` kernel test robot
2020-10-24 3:12 ` Jingoo Han
@ 2020-10-26 19:14 ` Rob Herring
2020-10-27 12:04 ` Marek Szyprowski
2 siblings, 1 reply; 20+ messages in thread
From: Rob Herring @ 2020-10-26 19:14 UTC (permalink / raw)
To: Marek Szyprowski
Cc: linux-samsung-soc, PCI, devicetree, linux-kernel@vger.kernel.org,
Jaehoon Chung, Jingoo Han, Krzysztof Kozlowski, Bjorn Helgaas,
Lorenzo Pieralisi, Vinod Koul, Kishon Vijay Abraham I
On Fri, Oct 23, 2020 at 2:58 AM Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
>
> From: Jaehoon Chung <jh80.chung@samsung.com>
>
> Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM:
> dts: exynos: Remove Exynos5440"). Rework this driver to support DWC PCIe
> variant found in the Exynos5433 SoCs.
>
> The main difference in Exynos5433 variant is lack of the MSI support
> (the MSI interrupt is not even routed to the CPU).
>
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
> [mszyprow: reworked the driver to support only Exynos5433 variant,
> simplified code, rebased onto current kernel code, added
> regulator support, converted to the regular platform driver,
> removed MSI related code, rewrote commit message]
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
> drivers/pci/controller/dwc/Kconfig | 3 +-
> drivers/pci/controller/dwc/pci-exynos.c | 358 ++++++++++--------------
> drivers/pci/quirks.c | 1 +
> 3 files changed, 145 insertions(+), 217 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
> index bc049865f8e0..ade07abd23c9 100644
> --- a/drivers/pci/controller/dwc/Kconfig
> +++ b/drivers/pci/controller/dwc/Kconfig
> @@ -84,8 +84,7 @@ config PCIE_DW_PLAT_EP
>
> config PCI_EXYNOS
> bool "Samsung Exynos PCIe controller"
> - depends on SOC_EXYNOS5440 || COMPILE_TEST
> - depends on PCI_MSI_IRQ_DOMAIN
> + depends on ARCH_EXYNOS || COMPILE_TEST
> select PCIE_DW_HOST
>
> config PCI_IMX6
> diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controller/dwc/pci-exynos.c
> index 242683cde04a..58056fbdc2fa 100644
> --- a/drivers/pci/controller/dwc/pci-exynos.c
> +++ b/drivers/pci/controller/dwc/pci-exynos.c
> @@ -2,26 +2,23 @@
> /*
> * PCIe host controller driver for Samsung Exynos SoCs
> *
> - * Copyright (C) 2013 Samsung Electronics Co., Ltd.
> + * Copyright (C) 2013-2020 Samsung Electronics Co., Ltd.
> * https://www.samsung.com
> *
> * Author: Jingoo Han <jg1.han@samsung.com>
> + * Jaehoon Chung <jh80.chung@samsung.com>
> */
>
> #include <linux/clk.h>
> #include <linux/delay.h>
> -#include <linux/gpio.h>
> #include <linux/interrupt.h>
> #include <linux/kernel.h>
> #include <linux/init.h>
> #include <linux/of_device.h>
> -#include <linux/of_gpio.h>
> #include <linux/pci.h>
> #include <linux/platform_device.h>
> #include <linux/phy/phy.h>
> -#include <linux/resource.h>
> -#include <linux/signal.h>
> -#include <linux/types.h>
> +#include <linux/regulator/consumer.h>
>
> #include "pcie-designware.h"
>
> @@ -37,102 +34,47 @@
> #define PCIE_IRQ_SPECIAL 0x008
> #define PCIE_IRQ_EN_PULSE 0x00c
> #define PCIE_IRQ_EN_LEVEL 0x010
> -#define IRQ_MSI_ENABLE BIT(2)
> #define PCIE_IRQ_EN_SPECIAL 0x014
> -#define PCIE_PWR_RESET 0x018
> +#define PCIE_SW_WAKE 0x018
> +#define PCIE_BUS_EN BIT(1)
> #define PCIE_CORE_RESET 0x01c
> #define PCIE_CORE_RESET_ENABLE BIT(0)
> #define PCIE_STICKY_RESET 0x020
> #define PCIE_NONSTICKY_RESET 0x024
> #define PCIE_APP_INIT_RESET 0x028
> #define PCIE_APP_LTSSM_ENABLE 0x02c
> -#define PCIE_ELBI_RDLH_LINKUP 0x064
> +#define PCIE_ELBI_RDLH_LINKUP 0x074
> +#define PCIE_ELBI_XMLH_LINKUP BIT(4)
> #define PCIE_ELBI_LTSSM_ENABLE 0x1
> #define PCIE_ELBI_SLV_AWMISC 0x11c
> #define PCIE_ELBI_SLV_ARMISC 0x120
> #define PCIE_ELBI_SLV_DBI_ENABLE BIT(21)
>
> -struct exynos_pcie_mem_res {
> - void __iomem *elbi_base; /* DT 0th resource: PCIe CTRL */
> -};
> -
> -struct exynos_pcie_clk_res {
> - struct clk *clk;
> - struct clk *bus_clk;
> -};
> +/* DBI register */
> +#define PCIE_MISC_CONTROL_1_OFF 0x8BC
> +#define DBI_RO_WR_EN BIT(0)
Standard DWC port logic register. The core already handles this
mostly. And provides a function to it where it doesn't. Looking at
your use, I think you can drop the access.
> struct exynos_pcie {
> - struct dw_pcie *pci;
> - struct exynos_pcie_mem_res *mem_res;
> - struct exynos_pcie_clk_res *clk_res;
> - const struct exynos_pcie_ops *ops;
> - int reset_gpio;
> -
> + struct dw_pcie pci;
> + void __iomem *elbi_base;
> + struct clk *clk;
> + struct clk *bus_clk;
> struct phy *phy;
> + struct regulator_bulk_data supplies[2];
> };
>
> -struct exynos_pcie_ops {
> - int (*get_mem_resources)(struct platform_device *pdev,
> - struct exynos_pcie *ep);
> - int (*get_clk_resources)(struct exynos_pcie *ep);
> - int (*init_clk_resources)(struct exynos_pcie *ep);
> - void (*deinit_clk_resources)(struct exynos_pcie *ep);
> -};
> -
> -static int exynos5440_pcie_get_mem_resources(struct platform_device *pdev,
> - struct exynos_pcie *ep)
> -{
> - struct dw_pcie *pci = ep->pci;
> - struct device *dev = pci->dev;
> -
> - ep->mem_res = devm_kzalloc(dev, sizeof(*ep->mem_res), GFP_KERNEL);
> - if (!ep->mem_res)
> - return -ENOMEM;
> -
> - ep->mem_res->elbi_base = devm_platform_ioremap_resource(pdev, 0);
> - if (IS_ERR(ep->mem_res->elbi_base))
> - return PTR_ERR(ep->mem_res->elbi_base);
> -
> - return 0;
> -}
> -
> -static int exynos5440_pcie_get_clk_resources(struct exynos_pcie *ep)
> -{
> - struct dw_pcie *pci = ep->pci;
> - struct device *dev = pci->dev;
> -
> - ep->clk_res = devm_kzalloc(dev, sizeof(*ep->clk_res), GFP_KERNEL);
> - if (!ep->clk_res)
> - return -ENOMEM;
> -
> - ep->clk_res->clk = devm_clk_get(dev, "pcie");
> - if (IS_ERR(ep->clk_res->clk)) {
> - dev_err(dev, "Failed to get pcie rc clock\n");
> - return PTR_ERR(ep->clk_res->clk);
> - }
> -
> - ep->clk_res->bus_clk = devm_clk_get(dev, "pcie_bus");
> - if (IS_ERR(ep->clk_res->bus_clk)) {
> - dev_err(dev, "Failed to get pcie bus clock\n");
> - return PTR_ERR(ep->clk_res->bus_clk);
> - }
> -
> - return 0;
> -}
> -
> -static int exynos5440_pcie_init_clk_resources(struct exynos_pcie *ep)
> +static int exynos_pcie_init_clk_resources(struct exynos_pcie *ep)
> {
> - struct dw_pcie *pci = ep->pci;
> - struct device *dev = pci->dev;
> + struct device *dev = ep->pci.dev;
> int ret;
>
> - ret = clk_prepare_enable(ep->clk_res->clk);
> + ret = clk_prepare_enable(ep->clk);
> if (ret) {
> dev_err(dev, "cannot enable pcie rc clock");
> return ret;
> }
>
> - ret = clk_prepare_enable(ep->clk_res->bus_clk);
> + ret = clk_prepare_enable(ep->bus_clk);
> if (ret) {
> dev_err(dev, "cannot enable pcie bus clock");
> goto err_bus_clk;
> @@ -141,24 +83,17 @@ static int exynos5440_pcie_init_clk_resources(struct exynos_pcie *ep)
> return 0;
>
> err_bus_clk:
> - clk_disable_unprepare(ep->clk_res->clk);
> + clk_disable_unprepare(ep->clk);
>
> return ret;
> }
>
> -static void exynos5440_pcie_deinit_clk_resources(struct exynos_pcie *ep)
> +static void exynos_pcie_deinit_clk_resources(struct exynos_pcie *ep)
> {
> - clk_disable_unprepare(ep->clk_res->bus_clk);
> - clk_disable_unprepare(ep->clk_res->clk);
> + clk_disable_unprepare(ep->bus_clk);
> + clk_disable_unprepare(ep->clk);
> }
>
> -static const struct exynos_pcie_ops exynos5440_pcie_ops = {
> - .get_mem_resources = exynos5440_pcie_get_mem_resources,
> - .get_clk_resources = exynos5440_pcie_get_clk_resources,
> - .init_clk_resources = exynos5440_pcie_init_clk_resources,
> - .deinit_clk_resources = exynos5440_pcie_deinit_clk_resources,
> -};
> -
> static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg)
> {
> writel(val, base + reg);
> @@ -173,67 +108,57 @@ static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *ep, bool on)
> {
> u32 val;
>
> - val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_ELBI_SLV_AWMISC);
> + val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_AWMISC);
> if (on)
> val |= PCIE_ELBI_SLV_DBI_ENABLE;
> else
> val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
> - exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_ELBI_SLV_AWMISC);
> + exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_AWMISC);
> }
>
> static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *ep, bool on)
> {
> u32 val;
>
> - val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_ELBI_SLV_ARMISC);
> + val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_ARMISC);
> if (on)
> val |= PCIE_ELBI_SLV_DBI_ENABLE;
> else
> val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
> - exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_ELBI_SLV_ARMISC);
> + exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_ARMISC);
> }
>
> static void exynos_pcie_assert_core_reset(struct exynos_pcie *ep)
> {
> u32 val;
>
> - val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_CORE_RESET);
> + val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET);
> val &= ~PCIE_CORE_RESET_ENABLE;
> - exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_CORE_RESET);
> - exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_PWR_RESET);
> - exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_STICKY_RESET);
> - exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_NONSTICKY_RESET);
> + exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET);
> + exynos_pcie_writel(ep->elbi_base, 0, PCIE_STICKY_RESET);
> + exynos_pcie_writel(ep->elbi_base, 0, PCIE_NONSTICKY_RESET);
> }
>
> static void exynos_pcie_deassert_core_reset(struct exynos_pcie *ep)
> {
> u32 val;
>
> - val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_CORE_RESET);
> + val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET);
> val |= PCIE_CORE_RESET_ENABLE;
>
> - exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_CORE_RESET);
> - exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_STICKY_RESET);
> - exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_NONSTICKY_RESET);
> - exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_APP_INIT_RESET);
> - exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_APP_INIT_RESET);
> -}
> -
> -static void exynos_pcie_assert_reset(struct exynos_pcie *ep)
> -{
> - struct dw_pcie *pci = ep->pci;
> - struct device *dev = pci->dev;
> -
> - if (ep->reset_gpio >= 0)
> - devm_gpio_request_one(dev, ep->reset_gpio,
> - GPIOF_OUT_INIT_HIGH, "RESET");
> + exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET);
> + exynos_pcie_writel(ep->elbi_base, 1, PCIE_STICKY_RESET);
> + exynos_pcie_writel(ep->elbi_base, 1, PCIE_NONSTICKY_RESET);
> + exynos_pcie_writel(ep->elbi_base, 1, PCIE_APP_INIT_RESET);
> + exynos_pcie_writel(ep->elbi_base, 0, PCIE_APP_INIT_RESET);
> }
>
> static int exynos_pcie_establish_link(struct exynos_pcie *ep)
> {
> - struct dw_pcie *pci = ep->pci;
> + struct dw_pcie *pci = &ep->pci;
> struct pcie_port *pp = &pci->pp;
> struct device *dev = pci->dev;
> + u32 val;
>
> if (dw_pcie_link_up(pci)) {
> dev_err(dev, "Link already up\n");
> @@ -243,19 +168,25 @@ static int exynos_pcie_establish_link(struct exynos_pcie *ep)
> exynos_pcie_assert_core_reset(ep);
>
> phy_reset(ep->phy);
> -
> - exynos_pcie_writel(ep->mem_res->elbi_base, 1,
> - PCIE_PWR_RESET);
> -
> phy_power_on(ep->phy);
> phy_init(ep->phy);
>
> exynos_pcie_deassert_core_reset(ep);
> +
> + val = exynos_pcie_readl(ep->elbi_base, PCIE_SW_WAKE);
> + val &= ~PCIE_BUS_EN;
> + exynos_pcie_writel(ep->elbi_base, val, PCIE_SW_WAKE);
> +
> + /*
> + * Enable DBI_RO_WR_EN bit.
> + * - When set to 1, some RO and HWinit bits are wriatble from
> + * the local application through the DBI.
> + */
> + dw_pcie_writel_dbi(pci, PCIE_MISC_CONTROL_1_OFF, DBI_RO_WR_EN);
> dw_pcie_setup_rc(pp);
First thing this function does is set DBI_RO_WR_EN.
> - exynos_pcie_assert_reset(ep);
>
> /* assert LTSSM enable */
> - exynos_pcie_writel(ep->mem_res->elbi_base, PCIE_ELBI_LTSSM_ENABLE,
> + exynos_pcie_writel(ep->elbi_base, PCIE_ELBI_LTSSM_ENABLE,
> PCIE_APP_LTSSM_ENABLE);
>
> /* check if the link is up or not */
> @@ -270,18 +201,8 @@ static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *ep)
> {
> u32 val;
>
> - val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_IRQ_PULSE);
> - exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_PULSE);
> -}
> -
> -static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep)
> -{
> - u32 val;
> -
> - /* enable INTX interrupt */
> - val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
> - IRQ_INTC_ASSERT | IRQ_INTD_ASSERT;
> - exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_EN_PULSE);
> + val = exynos_pcie_readl(ep->elbi_base, PCIE_IRQ_PULSE);
> + exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_PULSE);
> }
>
> static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)
> @@ -292,26 +213,14 @@ static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)
> return IRQ_HANDLED;
> }
>
> -static void exynos_pcie_msi_init(struct exynos_pcie *ep)
> -{
> - struct dw_pcie *pci = ep->pci;
> - struct pcie_port *pp = &pci->pp;
> - u32 val;
> -
> - dw_pcie_msi_init(pp);
> -
> - /* enable MSI interrupt */
> - val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_IRQ_EN_LEVEL);
> - val |= IRQ_MSI_ENABLE;
> - exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_EN_LEVEL);
> -}
> -
> -static void exynos_pcie_enable_interrupts(struct exynos_pcie *ep)
> +static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep)
> {
> - exynos_pcie_enable_irq_pulse(ep);
> + u32 val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
> + IRQ_INTC_ASSERT | IRQ_INTD_ASSERT;
>
> - if (IS_ENABLED(CONFIG_PCI_MSI))
> - exynos_pcie_msi_init(ep);
> + exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_EN_PULSE);
> + exynos_pcie_writel(ep->elbi_base, 0, PCIE_IRQ_EN_LEVEL);
> + exynos_pcie_writel(ep->elbi_base, 0, PCIE_IRQ_EN_SPECIAL);
> }
>
> static u32 exynos_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
> @@ -372,11 +281,8 @@ static int exynos_pcie_link_up(struct dw_pcie *pci)
> struct exynos_pcie *ep = to_exynos_pcie(pci);
> u32 val;
>
> - val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_ELBI_RDLH_LINKUP);
> - if (val == PCIE_ELBI_LTSSM_ENABLE)
> - return 1;
> -
> - return 0;
> + val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_RDLH_LINKUP);
> + return (val & PCIE_ELBI_XMLH_LINKUP);
> }
>
> static int exynos_pcie_host_init(struct pcie_port *pp)
> @@ -386,10 +292,8 @@ static int exynos_pcie_host_init(struct pcie_port *pp)
>
> pp->bridge->ops = &exynos_pci_ops;
>
> - exynos_pcie_establish_link(ep);
> - exynos_pcie_enable_interrupts(ep);
> -
> - return 0;
> + exynos_pcie_enable_irq_pulse(ep);
> + return exynos_pcie_establish_link(ep);
> }
>
> static const struct dw_pcie_host_ops exynos_pcie_host_ops = {
> @@ -399,28 +303,22 @@ static const struct dw_pcie_host_ops exynos_pcie_host_ops = {
> static int __init exynos_add_pcie_port(struct exynos_pcie *ep,
> struct platform_device *pdev)
> {
> - struct dw_pcie *pci = ep->pci;
> + struct dw_pcie *pci = &ep->pci;
> struct pcie_port *pp = &pci->pp;
> struct device *dev = &pdev->dev;
> int ret;
>
> - pp->irq = platform_get_irq(pdev, 1);
> + pp->irq = platform_get_irq(pdev, 0);
> if (pp->irq < 0)
> return pp->irq;
>
> ret = devm_request_irq(dev, pp->irq, exynos_pcie_irq_handler,
> - IRQF_SHARED, "exynos-pcie", ep);
> + IRQF_SHARED, "exynos-pcie", ep);
> if (ret) {
> dev_err(dev, "failed to request irq\n");
> return ret;
> }
>
> - if (IS_ENABLED(CONFIG_PCI_MSI)) {
> - pp->msi_irq = platform_get_irq(pdev, 0);
> - if (pp->msi_irq < 0)
> - return pp->msi_irq;
> - }
> -
> pp->ops = &exynos_pcie_host_ops;
>
> ret = dw_pcie_host_init(pp);
> @@ -438,10 +336,9 @@ static const struct dw_pcie_ops dw_pcie_ops = {
> .link_up = exynos_pcie_link_up,
> };
>
> -static int __init exynos_pcie_probe(struct platform_device *pdev)
> +static int exynos_pcie_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> - struct dw_pcie *pci;
> struct exynos_pcie *ep;
> struct device_node *np = dev->of_node;
> int ret;
> @@ -450,42 +347,49 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
> if (!ep)
> return -ENOMEM;
>
> - pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
> - if (!pci)
> - return -ENOMEM;
> -
> - pci->dev = dev;
> - pci->ops = &dw_pcie_ops;
> + ep->pci.dev = dev;
> + ep->pci.ops = &dw_pcie_ops;
>
> - ep->pci = pci;
> - ep->ops = (const struct exynos_pcie_ops *)
> - of_device_get_match_data(dev);
> + ep->phy = devm_of_phy_get(dev, np, NULL);
> + if (IS_ERR(ep->phy))
> + return PTR_ERR(ep->phy);
>
> - ep->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
> + /* External Local Bus interface (ELBI) registers */
> + ep->elbi_base = devm_platform_ioremap_resource_byname(pdev, "elbi");
> + if (IS_ERR(ep->elbi_base))
> + return PTR_ERR(ep->elbi_base);
>
> - ep->phy = devm_of_phy_get(dev, np, NULL);
> - if (IS_ERR(ep->phy)) {
> - if (PTR_ERR(ep->phy) != -ENODEV)
> - return PTR_ERR(ep->phy);
> + /* Data Bus Interface (DBI) registers */
> + ep->pci.dbi_base = devm_platform_ioremap_resource_byname(pdev, "dbi");
> + if (IS_ERR(ep->pci.dbi_base))
> + return PTR_ERR(ep->pci.dbi_base);
This is going to get moved to the DWC core code.
>
> - ep->phy = NULL;
> + ep->clk = devm_clk_get(dev, "pcie");
> + if (IS_ERR(ep->clk)) {
> + dev_err(dev, "Failed to get pcie rc clock\n");
> + return PTR_ERR(ep->clk);
> }
>
> - if (ep->ops && ep->ops->get_mem_resources) {
> - ret = ep->ops->get_mem_resources(pdev, ep);
> - if (ret)
> - return ret;
> + ep->bus_clk = devm_clk_get(dev, "pcie_bus");
> + if (IS_ERR(ep->bus_clk)) {
> + dev_err(dev, "Failed to get pcie bus clock\n");
> + return PTR_ERR(ep->bus_clk);
> }
>
> - if (ep->ops && ep->ops->get_clk_resources &&
> - ep->ops->init_clk_resources) {
> - ret = ep->ops->get_clk_resources(ep);
> - if (ret)
> - return ret;
> - ret = ep->ops->init_clk_resources(ep);
> - if (ret)
> - return ret;
> - }
> + ep->supplies[0].supply = "vdd18";
> + ep->supplies[1].supply = "vdd10";
> + ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ep->supplies),
> + ep->supplies);
> + if (ret)
> + return ret;
> +
> + ret = exynos_pcie_init_clk_resources(ep);
> + if (ret)
> + return ret;
> +
> + ret = regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep->supplies);
> + if (ret)
> + return ret;
>
> platform_set_drvdata(pdev, ep);
>
> @@ -497,9 +401,9 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
>
> fail_probe:
> phy_exit(ep->phy);
> + exynos_pcie_deinit_clk_resources(ep);
> + regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies);
>
> - if (ep->ops && ep->ops->deinit_clk_resources)
> - ep->ops->deinit_clk_resources(ep);
> return ret;
> }
>
> @@ -507,32 +411,56 @@ static int __exit exynos_pcie_remove(struct platform_device *pdev)
> {
> struct exynos_pcie *ep = platform_get_drvdata(pdev);
>
> - if (ep->ops && ep->ops->deinit_clk_resources)
> - ep->ops->deinit_clk_resources(ep);
> + phy_power_off(ep->phy);
> + phy_exit(ep->phy);
> + exynos_pcie_deinit_clk_resources(ep);
> + regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies);
>
> return 0;
> }
>
> +static int __maybe_unused exynos_pcie_suspend_noirq(struct device *dev)
> +{
Why noirq variant needed? Lot's of PCI host drivers do this and I've
yet to get a reason...
Adding suspend/resume should probably be a separate patch. What I'd
like to do here is have common DWC suspend/resume functions that the
platform drivers can use or wrap.
> + struct exynos_pcie *ep = dev_get_drvdata(dev);
> +
> + phy_power_off(ep->phy);
> + phy_exit(ep->phy);
> + regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies);
> +
> + return 0;
> +}
> +
> +static int __maybe_unused exynos_pcie_resume_noirq(struct device *dev)
> +{
> + struct exynos_pcie *ep = dev_get_drvdata(dev);
> + struct dw_pcie *pci = &ep->pci;
> + struct pcie_port *pp = &pci->pp;
> + int ret;
> +
> + ret = regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep->supplies);
> + if (ret)
> + return ret;
> + /* exynos_pcie_host_init controls ep->phy */
> + return exynos_pcie_host_init(pp);
> +}
> +
> +static const struct dev_pm_ops exynos_pcie_pm_ops = {
> + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(exynos_pcie_suspend_noirq,
> + exynos_pcie_resume_noirq)
> +};
> +
> static const struct of_device_id exynos_pcie_of_match[] = {
> - {
> - .compatible = "samsung,exynos5440-pcie",
> - .data = &exynos5440_pcie_ops
> - },
> - {},
> + { .compatible = "samsung,exynos5433-pcie", },
> + { },
> };
>
> static struct platform_driver exynos_pcie_driver = {
> + .probe = exynos_pcie_probe,
> .remove = __exit_p(exynos_pcie_remove),
> .driver = {
> .name = "exynos-pcie",
> .of_match_table = exynos_pcie_of_match,
> + .pm = &exynos_pcie_pm_ops,
> },
> };
> -
> -/* Exynos PCIe driver does not allow module unload */
> -
> -static int __init exynos_pcie_init(void)
> -{
> - return platform_driver_probe(&exynos_pcie_driver, exynos_pcie_probe);
> -}
> -subsys_initcall(exynos_pcie_init);
Good that this is gone, but...
> +builtin_platform_driver(exynos_pcie_driver);
I would like to make all the host drivers modules.
Rob
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v2 5/6] pci: dwc: pci-exynos: rework the driver to support Exynos5433 variant
2020-10-26 19:14 ` Rob Herring
@ 2020-10-27 12:04 ` Marek Szyprowski
2020-10-27 13:24 ` Marek Szyprowski
0 siblings, 1 reply; 20+ messages in thread
From: Marek Szyprowski @ 2020-10-27 12:04 UTC (permalink / raw)
To: Rob Herring
Cc: linux-samsung-soc, PCI, devicetree, linux-kernel@vger.kernel.org,
Jaehoon Chung, Jingoo Han, Krzysztof Kozlowski, Bjorn Helgaas,
Lorenzo Pieralisi, Vinod Koul, Kishon Vijay Abraham I
Hi Rob,
On 26.10.2020 20:14, Rob Herring wrote:
> On Fri, Oct 23, 2020 at 2:58 AM Marek Szyprowski
> <m.szyprowski@samsung.com> wrote:
>> From: Jaehoon Chung <jh80.chung@samsung.com>
>>
>> Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM:
>> dts: exynos: Remove Exynos5440"). Rework this driver to support DWC PCIe
>> variant found in the Exynos5433 SoCs.
>>
>> The main difference in Exynos5433 variant is lack of the MSI support
>> (the MSI interrupt is not even routed to the CPU).
>>
>> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
>> [mszyprow: reworked the driver to support only Exynos5433 variant,
>> simplified code, rebased onto current kernel code, added
>> regulator support, converted to the regular platform driver,
>> removed MSI related code, rewrote commit message]
>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
>> ---
>> drivers/pci/controller/dwc/Kconfig | 3 +-
>> drivers/pci/controller/dwc/pci-exynos.c | 358 ++++++++++--------------
>> drivers/pci/quirks.c | 1 +
>> 3 files changed, 145 insertions(+), 217 deletions(-)
>>
>> diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
>> index bc049865f8e0..ade07abd23c9 100644
>> --- a/drivers/pci/controller/dwc/Kconfig
>> +++ b/drivers/pci/controller/dwc/Kconfig
>> @@ -84,8 +84,7 @@ config PCIE_DW_PLAT_EP
>>
>> config PCI_EXYNOS
>> bool "Samsung Exynos PCIe controller"
>> - depends on SOC_EXYNOS5440 || COMPILE_TEST
>> - depends on PCI_MSI_IRQ_DOMAIN
>> + depends on ARCH_EXYNOS || COMPILE_TEST
>> select PCIE_DW_HOST
>>
>> config PCI_IMX6
>> diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controller/dwc/pci-exynos.c
>> index 242683cde04a..58056fbdc2fa 100644
>> --- a/drivers/pci/controller/dwc/pci-exynos.c
>> +++ b/drivers/pci/controller/dwc/pci-exynos.c
>> @@ -2,26 +2,23 @@
>> /*
>> * PCIe host controller driver for Samsung Exynos SoCs
>> *
>> - * Copyright (C) 2013 Samsung Electronics Co., Ltd.
>> + * Copyright (C) 2013-2020 Samsung Electronics Co., Ltd.
>> * https://www.samsung.com
>> *
>> * Author: Jingoo Han <jg1.han@samsung.com>
>> + * Jaehoon Chung <jh80.chung@samsung.com>
>> */
>>
>> #include <linux/clk.h>
>> #include <linux/delay.h>
>> -#include <linux/gpio.h>
>> #include <linux/interrupt.h>
>> #include <linux/kernel.h>
>> #include <linux/init.h>
>> #include <linux/of_device.h>
>> -#include <linux/of_gpio.h>
>> #include <linux/pci.h>
>> #include <linux/platform_device.h>
>> #include <linux/phy/phy.h>
>> -#include <linux/resource.h>
>> -#include <linux/signal.h>
>> -#include <linux/types.h>
>> +#include <linux/regulator/consumer.h>
>>
>> #include "pcie-designware.h"
>>
>> @@ -37,102 +34,47 @@
>> #define PCIE_IRQ_SPECIAL 0x008
>> #define PCIE_IRQ_EN_PULSE 0x00c
>> #define PCIE_IRQ_EN_LEVEL 0x010
>> -#define IRQ_MSI_ENABLE BIT(2)
>> #define PCIE_IRQ_EN_SPECIAL 0x014
>> -#define PCIE_PWR_RESET 0x018
>> +#define PCIE_SW_WAKE 0x018
>> +#define PCIE_BUS_EN BIT(1)
>> #define PCIE_CORE_RESET 0x01c
>> #define PCIE_CORE_RESET_ENABLE BIT(0)
>> #define PCIE_STICKY_RESET 0x020
>> #define PCIE_NONSTICKY_RESET 0x024
>> #define PCIE_APP_INIT_RESET 0x028
>> #define PCIE_APP_LTSSM_ENABLE 0x02c
>> -#define PCIE_ELBI_RDLH_LINKUP 0x064
>> +#define PCIE_ELBI_RDLH_LINKUP 0x074
>> +#define PCIE_ELBI_XMLH_LINKUP BIT(4)
>> #define PCIE_ELBI_LTSSM_ENABLE 0x1
>> #define PCIE_ELBI_SLV_AWMISC 0x11c
>> #define PCIE_ELBI_SLV_ARMISC 0x120
>> #define PCIE_ELBI_SLV_DBI_ENABLE BIT(21)
>>
>> -struct exynos_pcie_mem_res {
>> - void __iomem *elbi_base; /* DT 0th resource: PCIe CTRL */
>> -};
>> -
>> -struct exynos_pcie_clk_res {
>> - struct clk *clk;
>> - struct clk *bus_clk;
>> -};
>> +/* DBI register */
>> +#define PCIE_MISC_CONTROL_1_OFF 0x8BC
>> +#define DBI_RO_WR_EN BIT(0)
> Standard DWC port logic register. The core already handles this
> mostly. And provides a function to it where it doesn't. Looking at
> your use, I think you can drop the access.
>
>> ...
>> @@ -243,19 +168,25 @@ static int exynos_pcie_establish_link(struct exynos_pcie *ep)
>> exynos_pcie_assert_core_reset(ep);
>>
>> phy_reset(ep->phy);
>> -
>> - exynos_pcie_writel(ep->mem_res->elbi_base, 1,
>> - PCIE_PWR_RESET);
>> -
>> phy_power_on(ep->phy);
>> phy_init(ep->phy);
>>
>> exynos_pcie_deassert_core_reset(ep);
>> +
>> + val = exynos_pcie_readl(ep->elbi_base, PCIE_SW_WAKE);
>> + val &= ~PCIE_BUS_EN;
>> + exynos_pcie_writel(ep->elbi_base, val, PCIE_SW_WAKE);
>> +
>> + /*
>> + * Enable DBI_RO_WR_EN bit.
>> + * - When set to 1, some RO and HWinit bits are wriatble from
>> + * the local application through the DBI.
>> + */
>> + dw_pcie_writel_dbi(pci, PCIE_MISC_CONTROL_1_OFF, DBI_RO_WR_EN);
>> dw_pcie_setup_rc(pp);
> First thing this function does is set DBI_RO_WR_EN.
Indeed, this has been added to dw_pcie_setup_rc() in commit 3924bc2fd1b6
("PCI: dwc: Group DBI registers writes requiring unlocking"), after
initial version of this patchset. Thanks for pointing this out. I will
remove this.
>> ...
>> @@ -450,42 +347,49 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
>> if (!ep)
>> return -ENOMEM;
>>
>> - pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
>> - if (!pci)
>> - return -ENOMEM;
>> -
>> - pci->dev = dev;
>> - pci->ops = &dw_pcie_ops;
>> + ep->pci.dev = dev;
>> + ep->pci.ops = &dw_pcie_ops;
>>
>> - ep->pci = pci;
>> - ep->ops = (const struct exynos_pcie_ops *)
>> - of_device_get_match_data(dev);
>> + ep->phy = devm_of_phy_get(dev, np, NULL);
>> + if (IS_ERR(ep->phy))
>> + return PTR_ERR(ep->phy);
>>
>> - ep->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
>> + /* External Local Bus interface (ELBI) registers */
>> + ep->elbi_base = devm_platform_ioremap_resource_byname(pdev, "elbi");
>> + if (IS_ERR(ep->elbi_base))
>> + return PTR_ERR(ep->elbi_base);
>>
>> - ep->phy = devm_of_phy_get(dev, np, NULL);
>> - if (IS_ERR(ep->phy)) {
>> - if (PTR_ERR(ep->phy) != -ENODEV)
>> - return PTR_ERR(ep->phy);
>> + /* Data Bus Interface (DBI) registers */
>> + ep->pci.dbi_base = devm_platform_ioremap_resource_byname(pdev, "dbi");
>> + if (IS_ERR(ep->pci.dbi_base))
>> + return PTR_ERR(ep->pci.dbi_base);
> This is going to get moved to the DWC core code.
Well, so far it is not there yet and other dw-pci drivers do it on their
own. Could you point a patch that does this, so I can rebase onto it?
>
>> - ep->phy = NULL;
>> + ep->clk = devm_clk_get(dev, "pcie");
>> + if (IS_ERR(ep->clk)) {
>> + dev_err(dev, "Failed to get pcie rc clock\n");
>> + return PTR_ERR(ep->clk);
>> }
>>
>> - if (ep->ops && ep->ops->get_mem_resources) {
>> - ret = ep->ops->get_mem_resources(pdev, ep);
>> - if (ret)
>> - return ret;
>> + ep->bus_clk = devm_clk_get(dev, "pcie_bus");
>> + if (IS_ERR(ep->bus_clk)) {
>> + dev_err(dev, "Failed to get pcie bus clock\n");
>> + return PTR_ERR(ep->bus_clk);
>> }
>>
>> - if (ep->ops && ep->ops->get_clk_resources &&
>> - ep->ops->init_clk_resources) {
>> - ret = ep->ops->get_clk_resources(ep);
>> - if (ret)
>> - return ret;
>> - ret = ep->ops->init_clk_resources(ep);
>> - if (ret)
>> - return ret;
>> - }
>> + ep->supplies[0].supply = "vdd18";
>> + ep->supplies[1].supply = "vdd10";
>> + ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ep->supplies),
>> + ep->supplies);
>> + if (ret)
>> + return ret;
>> +
>> + ret = exynos_pcie_init_clk_resources(ep);
>> + if (ret)
>> + return ret;
>> +
>> + ret = regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep->supplies);
>> + if (ret)
>> + return ret;
>>
>> platform_set_drvdata(pdev, ep);
>>
>> @@ -497,9 +401,9 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
>>
>> fail_probe:
>> phy_exit(ep->phy);
>> + exynos_pcie_deinit_clk_resources(ep);
>> + regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies);
>>
>> - if (ep->ops && ep->ops->deinit_clk_resources)
>> - ep->ops->deinit_clk_resources(ep);
>> return ret;
>> }
>>
>> @@ -507,32 +411,56 @@ static int __exit exynos_pcie_remove(struct platform_device *pdev)
>> {
>> struct exynos_pcie *ep = platform_get_drvdata(pdev);
>>
>> - if (ep->ops && ep->ops->deinit_clk_resources)
>> - ep->ops->deinit_clk_resources(ep);
>> + phy_power_off(ep->phy);
>> + phy_exit(ep->phy);
>> + exynos_pcie_deinit_clk_resources(ep);
>> + regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies);
>>
>> return 0;
>> }
>>
>> +static int __maybe_unused exynos_pcie_suspend_noirq(struct device *dev)
>> +{
> Why noirq variant needed? Lot's of PCI host drivers do this and I've
> yet to get a reason...
Frankly, I have no idea, but switching to SET_LATE_SYSTEM_SLEEP_PM_OPS
breaks system suspend/resume operation - the board doesn't resume from
suspend. If this is really important I will add some more logs and try
to find what happens between late/early and noirq phases.
> Adding suspend/resume should probably be a separate patch. What I'd
> like to do here is have common DWC suspend/resume functions that the
> platform drivers can use or wrap.
Okay, I can move adding suspend/resume to the separate patch if You
want. However I probably know too little about PCI to extract some
common dwc suspend/resume functions.
>> + struct exynos_pcie *ep = dev_get_drvdata(dev);
>> +
>> + phy_power_off(ep->phy);
>> + phy_exit(ep->phy);
>> + regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies);
>> +
>> + return 0;
>> +}
>> +
>> +static int __maybe_unused exynos_pcie_resume_noirq(struct device *dev)
>> +{
>> + struct exynos_pcie *ep = dev_get_drvdata(dev);
>> + struct dw_pcie *pci = &ep->pci;
>> + struct pcie_port *pp = &pci->pp;
>> + int ret;
>> +
>> + ret = regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep->supplies);
>> + if (ret)
>> + return ret;
>> + /* exynos_pcie_host_init controls ep->phy */
>> + return exynos_pcie_host_init(pp);
>> +}
>> +
>> +static const struct dev_pm_ops exynos_pcie_pm_ops = {
>> + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(exynos_pcie_suspend_noirq,
>> + exynos_pcie_resume_noirq)
>> +};
>> +
>> static const struct of_device_id exynos_pcie_of_match[] = {
>> - {
>> - .compatible = "samsung,exynos5440-pcie",
>> - .data = &exynos5440_pcie_ops
>> - },
>> - {},
>> + { .compatible = "samsung,exynos5433-pcie", },
>> + { },
>> };
>>
>> static struct platform_driver exynos_pcie_driver = {
>> + .probe = exynos_pcie_probe,
>> .remove = __exit_p(exynos_pcie_remove),
>> .driver = {
>> .name = "exynos-pcie",
>> .of_match_table = exynos_pcie_of_match,
>> + .pm = &exynos_pcie_pm_ops,
>> },
>> };
>> -
>> -/* Exynos PCIe driver does not allow module unload */
>> -
>> -static int __init exynos_pcie_init(void)
>> -{
>> - return platform_driver_probe(&exynos_pcie_driver, exynos_pcie_probe);
>> -}
>> -subsys_initcall(exynos_pcie_init);
> Good that this is gone, but...
>
>> +builtin_platform_driver(exynos_pcie_driver);
> I would like to make all the host drivers modules.
I can check if this can be easily done. If not, I would like to keep it
builtin in this patch and leave modularization for the future.
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v2 5/6] pci: dwc: pci-exynos: rework the driver to support Exynos5433 variant
2020-10-27 12:04 ` Marek Szyprowski
@ 2020-10-27 13:24 ` Marek Szyprowski
0 siblings, 0 replies; 20+ messages in thread
From: Marek Szyprowski @ 2020-10-27 13:24 UTC (permalink / raw)
To: Rob Herring
Cc: linux-samsung-soc, PCI, devicetree, linux-kernel@vger.kernel.org,
Jaehoon Chung, Jingoo Han, Krzysztof Kozlowski, Bjorn Helgaas,
Lorenzo Pieralisi, Vinod Koul, Kishon Vijay Abraham I
Hi
On 27.10.2020 13:04, Marek Szyprowski wrote:
> On 26.10.2020 20:14, Rob Herring wrote:
>> On Fri, Oct 23, 2020 at 2:58 AM Marek Szyprowski
>> <m.szyprowski@samsung.com> wrote:
>>> From: Jaehoon Chung <jh80.chung@samsung.com>
>>>
>>> Exynos5440 SoC support has been dropped since commit 8c83315da1cf
>>> ("ARM:
>>> dts: exynos: Remove Exynos5440"). Rework this driver to support DWC
>>> PCIe
>>> variant found in the Exynos5433 SoCs.
>>>
>>> The main difference in Exynos5433 variant is lack of the MSI support
>>> (the MSI interrupt is not even routed to the CPU).
>>>
>>> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
>>> [mszyprow: reworked the driver to support only Exynos5433 variant,
>>> simplified code, rebased onto current kernel code, added
>>> regulator support, converted to the regular platform
>>> driver,
>>> removed MSI related code, rewrote commit message]
>>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>>> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
>>> ---
>>> drivers/pci/controller/dwc/Kconfig | 3 +-
>>> drivers/pci/controller/dwc/pci-exynos.c | 358
>>> ++++++++++--------------
>>> drivers/pci/quirks.c | 1 +
>>> 3 files changed, 145 insertions(+), 217 deletions(-)
...
>>> +static int __maybe_unused exynos_pcie_suspend_noirq(struct device
>>> *dev)
>>> +{
>> Why noirq variant needed? Lot's of PCI host drivers do this and I've
>> yet to get a reason...
> Frankly, I have no idea, but switching to SET_LATE_SYSTEM_SLEEP_PM_OPS
> breaks system suspend/resume operation - the board doesn't resume from
> suspend. If this is really important I will add some more logs and try
> to find what happens between late/early and noirq phases.
It looks that PCI framework does something with the device or controller
in noirq phase, so the driver cannot shutdown the controller earlier.
Here is a relevant part from the kernel log after system suspend/resume
cycle captured with init_calldebug enabled:
$ dmesg | grep pci
brcmfmac 0000:01:00.0: calling pci_pm_suspend+0x0/0x248 @ 96, parent:
0000:00:00.0
brcmfmac 0000:01:00.0: pci_pm_suspend+0x0/0x248 returned 0 after 650 usecs
pcieport 0000:00:00.0: calling pci_pm_suspend+0x0/0x248 @ 7, parent:
pci0000:00
pcieport 0000:00:00.0: pci_pm_suspend+0x0/0x248 returned 0 after 85 usecs
exynos-pcie 15700000.pcie: calling platform_pm_suspend+0x0/0x68 @ 447,
parent: soc@0
exynos-pcie 15700000.pcie: platform_pm_suspend+0x0/0x68 returned 0 after
4 usecs
exynos_pcie_phy 15680000.pcie-phy: calling platform_pm_suspend+0x0/0x68
@ 447, parent: soc@0
exynos_pcie_phy 15680000.pcie-phy: platform_pm_suspend+0x0/0x68 returned
0 after 3 usecs
brcmfmac 0000:01:00.0: calling pci_pm_suspend_late+0x0/0x50 @ 448,
parent: 0000:00:00.0
brcmfmac 0000:01:00.0: pci_pm_suspend_late+0x0/0x50 returned 0 after 4 usecs
pcieport 0000:00:00.0: calling pci_pm_suspend_late+0x0/0x50 @ 449,
parent: pci0000:00
pcieport 0000:00:00.0: pci_pm_suspend_late+0x0/0x50 returned 0 after 4 usecs
exynos-pcie 15700000.pcie: calling exynos_pcie_suspend_late+0x0/0x30 @
447, parent: soc@0
exynos-pcie 15700000.pcie: exynos_pcie_suspend_late 439
exynos-pcie 15700000.pcie: exynos_pcie_suspend_late+0x0/0x30 returned 0
after 17 usecs
brcmfmac 0000:01:00.0: calling pci_pm_suspend_noirq+0x0/0x278 @ 449,
parent: 0000:00:00.0
brcmfmac 0000:01:00.0: pci_pm_suspend_noirq+0x0/0x278 returned 0 after
24272 usecs
pcieport 0000:00:00.0: calling pci_pm_suspend_noirq+0x0/0x278 @ 448,
parent: pci0000:00
pcieport 0000:00:00.0: pci_pm_suspend_noirq+0x0/0x278 returned 0 after
196 usecs
exynos-pcie 15700000.pcie: calling exynos_pcie_suspend_noirq+0x0/0x40 @
447, parent: soc@0
exynos-pcie 15700000.pcie: exynos_pcie_suspend_noirq+0x0/0x40 returned 0
after 653 usecs
exynos-pcie 15700000.pcie: calling exynos_pcie_resume_noirq+0x0/0x38 @
447, parent: soc@0
exynos-pcie 15700000.pcie: Link up
exynos-pcie 15700000.pcie: exynos_pcie_resume_noirq+0x0/0x38 returned 0
after 91433 usecs
pcieport 0000:00:00.0: calling pci_pm_resume_noirq+0x0/0x140 @ 96,
parent: pci0000:00
pcieport 0000:00:00.0: pci_pm_resume_noirq+0x0/0x140 returned 0 after
316 usecs
brcmfmac 0000:01:00.0: calling pci_pm_resume_noirq+0x0/0x140 @ 143,
parent: 0000:00:00.0
brcmfmac 0000:01:00.0: pci_pm_resume_noirq+0x0/0x140 returned 0 after
25470 usecs
exynos-pcie 15700000.pcie: calling exynos_pcie_resume_late+0x0/0x30 @
447, parent: soc@0
exynos-pcie 15700000.pcie: exynos_pcie_resume_late 445
exynos-pcie 15700000.pcie: exynos_pcie_resume_late+0x0/0x30 returned 0
after 24 usecs
pcieport 0000:00:00.0: calling pci_pm_resume_early+0x0/0x48 @ 449,
parent: pci0000:00
pcieport 0000:00:00.0: pci_pm_resume_early+0x0/0x48 returned 0 after 3 usecs
brcmfmac 0000:01:00.0: calling pci_pm_resume_early+0x0/0x48 @ 448,
parent: 0000:00:00.0
brcmfmac 0000:01:00.0: pci_pm_resume_early+0x0/0x48 returned 0 after 3 usecs
exynos_pcie_phy 15680000.pcie-phy: calling platform_pm_resume+0x0/0x60 @
447, parent: soc@0
exynos_pcie_phy 15680000.pcie-phy: platform_pm_resume+0x0/0x60 returned
0 after 4 usecs
exynos-pcie 15700000.pcie: calling platform_pm_resume+0x0/0x60 @ 447,
parent: soc@0
exynos-pcie 15700000.pcie: platform_pm_resume+0x0/0x60 returned 0 after
4 usecs
pcieport 0000:00:00.0: calling pci_pm_resume+0x0/0xe0 @ 96, parent:
pci0000:00
pcieport 0000:00:00.0: pci_pm_resume+0x0/0xe0 returned 0 after 54 usecs
brcmfmac 0000:01:00.0: calling pci_pm_resume+0x0/0xe0 @ 142, parent:
0000:00:00.0
brcmfmac 0000:01:00.0: pci_pm_resume+0x0/0xe0 returned 0 after 554 usecs
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 6/6] arm64: dts: exynos: add the WiFi/PCIe support to TM2(e) boards
2020-10-23 7:57 ` [PATCH v2 0/6] Add DW PCIe support for Exynos5433 SoCs Marek Szyprowski
` (4 preceding siblings ...)
2020-10-23 7:57 ` [PATCH v2 5/6] pci: dwc: pci-exynos: rework the driver to support Exynos5433 variant Marek Szyprowski
@ 2020-10-23 7:57 ` Marek Szyprowski
5 siblings, 0 replies; 20+ messages in thread
From: Marek Szyprowski @ 2020-10-23 7:57 UTC (permalink / raw)
To: linux-samsung-soc, linux-pci
Cc: devicetree, linux-kernel, Jaehoon Chung, Marek Szyprowski,
Jingoo Han, Krzysztof Kozlowski, Bjorn Helgaas, Lorenzo Pieralisi,
Vinod Koul, Kishon Vijay Abraham I, Rob Herring
From: Jaehoon Chung <jh80.chung@samsung.com>
Add the nodes relevant to PCIe PHY and PCIe support. PCIe is used for the
WiFi interface (Broadcom Limited BCM4358 802.11ac Wireless LAN SoC).
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
[mszyprow: rewrote commit message, reworked board/generic dts/dtsi split]
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
.../boot/dts/exynos/exynos5433-pinctrl.dtsi | 2 +-
.../dts/exynos/exynos5433-tm2-common.dtsi | 24 ++++++++++++-
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 35 +++++++++++++++++++
3 files changed, 59 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
index 9df7c65593a1..32a6518517e5 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
@@ -329,7 +329,7 @@
};
pcie_bus: pcie_bus {
- samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7";
+ samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6";
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
};
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
index 829fea23d4ab..6e45a42be562 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
@@ -969,6 +969,25 @@
bus-width = <4>;
};
+&pcie {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_bus &pcie_wlanen>;
+ vdd10-supply = <&ldo6_reg>;
+ vdd18-supply = <&ldo7_reg>;
+ assigned-clocks = <&cmu_fsys CLK_MOUT_SCLK_PCIE_100_USER>,
+ <&cmu_top CLK_MOUT_SCLK_PCIE_100>;
+ assigned-clock-parents = <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
+ <&cmu_top CLK_MOUT_BUS_PLL_USER>;
+ assigned-clock-rates = <0>, <100000000>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
&ppmu_d0_general {
status = "okay";
events {
@@ -1085,8 +1104,11 @@
pinctrl-names = "default";
pinctrl-0 = <&initial_ese>;
+ pcie_wlanen: pcie-wlanen {
+ PIN(INPUT, gpj2-0, UP, FAST_SR4);
+ };
+
initial_ese: initial-state {
- PIN(INPUT, gpj2-0, DOWN, FAST_SR1);
PIN(INPUT, gpj2-1, DOWN, FAST_SR1);
PIN(INPUT, gpj2-2, DOWN, FAST_SR1);
};
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 8eb4576da8f3..4d25b7d2486c 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -1029,6 +1029,11 @@
reg = <0x145f0000 0x1038>;
};
+ syscon_fsys: syscon@156f0000 {
+ compatible = "syscon";
+ reg = <0x156f0000 0x1044>;
+ };
+
gsc_0: video-scaler@13c00000 {
compatible = "samsung,exynos5433-gsc";
reg = <0x13c00000 0x1000>;
@@ -1830,6 +1835,36 @@
status = "disabled";
};
};
+
+ pcie_phy: pcie-phy@15680000 {
+ compatible = "samsung,exynos5433-pcie-phy";
+ reg = <0x15680000 0x1000>;
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ samsung,fsys-sysreg = <&syscon_fsys>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ pcie: pcie@15700000 {
+ compatible = "samsung,exynos5433-pcie";
+ reg = <0x15700000 0x1000>, <0x156b0000 0x1000>,
+ <0x0c000000 0x1000>;
+ reg-names = "dbi", "elbi", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu_fsys CLK_PCIE>,
+ <&cmu_fsys CLK_PCLK_PCIE_PHY>;
+ clock-names = "pcie", "pcie_bus";
+ num-lanes = <1>;
+ bus-range = <0x00 0xff>;
+ phys = <&pcie_phy>;
+ ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>,
+ <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>;
+ status = "disabled";
+ };
};
timer: timer {
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread