Re: [PATCH 2/2] pinctrl: qcom: Add SDX55 pincontrol driver

[Vinod Koul <vkoul@kernel.org>]

On 28-10-20, 11:35, Bjorn Andersson wrote:
> On Wed 28 Oct 03:30 CDT 2020, Vinod Koul wrote:
> > diff --git a/drivers/pinctrl/qcom/pinctrl-sdx55.c b/drivers/pinctrl/qcom/pinctrl-sdx55.c
> [..]
> > +static const struct msm_function sdx55_functions[] = {
> [..]
> > +	FUNCTION(qdss_gpio),
> > +	FUNCTION(qdss_gpio0),
> > +	FUNCTION(qdss_gpio1),
> > +	FUNCTION(qdss_gpio2),
> > +	FUNCTION(qdss_gpio3),
> > +	FUNCTION(qdss_gpio4),
> > +	FUNCTION(qdss_gpio5),
> > +	FUNCTION(qdss_gpio6),
> > +	FUNCTION(qdss_gpio7),
> > +	FUNCTION(qdss_gpio8),
> > +	FUNCTION(qdss_gpio9),
> > +	FUNCTION(qdss_gpio10),
> > +	FUNCTION(qdss_gpio11),
> > +	FUNCTION(qdss_gpio12),
> > +	FUNCTION(qdss_gpio13),
> > +	FUNCTION(qdss_gpio14),
> > +	FUNCTION(qdss_gpio15),
> 
> As there are no overlaps within pingroups you can keep qdss_gpio as a
> single function.

Okay so is the generic guidance to group things into single function
when they do not overlap?

> 
> > +	FUNCTION(qdss_stm0),
> > +	FUNCTION(qdss_stm1),
> > +	FUNCTION(qdss_stm2),
> > +	FUNCTION(qdss_stm3),
> > +	FUNCTION(qdss_stm4),
> > +	FUNCTION(qdss_stm5),
> > +	FUNCTION(qdss_stm6),
> > +	FUNCTION(qdss_stm7),
> > +	FUNCTION(qdss_stm8),
> > +	FUNCTION(qdss_stm9),
> > +	FUNCTION(qdss_stm10),
> > +	FUNCTION(qdss_stm11),
> > +	FUNCTION(qdss_stm12),
> > +	FUNCTION(qdss_stm13),
> > +	FUNCTION(qdss_stm14),
> > +	FUNCTION(qdss_stm15),
> > +	FUNCTION(qdss_stm16),
> > +	FUNCTION(qdss_stm17),
> > +	FUNCTION(qdss_stm18),
> > +	FUNCTION(qdss_stm19),
> > +	FUNCTION(qdss_stm20),
> > +	FUNCTION(qdss_stm21),
> > +	FUNCTION(qdss_stm22),
> > +	FUNCTION(qdss_stm23),
> > +	FUNCTION(qdss_stm24),
> > +	FUNCTION(qdss_stm25),
> > +	FUNCTION(qdss_stm26),
> > +	FUNCTION(qdss_stm27),
> > +	FUNCTION(qdss_stm28),
> > +	FUNCTION(qdss_stm29),
> > +	FUNCTION(qdss_stm30),
> > +	FUNCTION(qdss_stm31),
> 
> Ditto.
> 
> > +	FUNCTION(qlink0_en),
> > +	FUNCTION(qlink0_req),
> > +	FUNCTION(qlink0_wmss),
> > +	FUNCTION(qlink1_en),
> > +	FUNCTION(qlink1_req),
> > +	FUNCTION(qlink1_wmss),
> > +	FUNCTION(spmi_coex),
> > +	FUNCTION(sec_mi2s),
> > +	FUNCTION(spmi_vgi),
> > +	FUNCTION(tgu_ch0),
> > +	FUNCTION(uim1_clk),
> > +	FUNCTION(uim1_data),
> > +	FUNCTION(uim1_present),
> > +	FUNCTION(uim1_reset),
> > +	FUNCTION(uim2_clk),
> > +	FUNCTION(uim2_data),
> > +	FUNCTION(uim2_present),
> > +	FUNCTION(uim2_reset),
> > +	FUNCTION(usb2phy_ac),
> > +	FUNCTION(vsense_trigger),
> > +};
> > +
> > +/* Every pin is maintained as a single group, and missing or non-existing pin
> > + * would be maintained as dummy group to synchronize pin group index with
> > + * pin descriptor registered with pinctrl core.
> > + * Clients would not be able to request these dummy pin groups.
> > + */
> > +static const struct msm_pingroup sdx55_groups[] = {
> > +	[0] = PINGROUP(0, uim2_data, blsp_uart1, qdss_stm31, ebi0_wrcdc, _,
> > +		       _, _, _, _),
> 
> Please break the 80 character suggestion and leave these unwrapped.

120 now ;-)

> 
> [..]
> > +	[108] = UFS_RESET(ufs_reset, 0x0),
> 
> SDX55 doesn't have UFS support and I'm not able to find any UFS_RESET
> register in the TLMM block. So I suspect this is a copy paste issue
> somewhere.
> 
> PS. Don't forget to drop the macro, if we don't need it.

I will check though I have not seen UFS block. But yes this did exist in
downstream!

> 
> > +	[109] = SDC_PINGROUP(sdc1_rclk, 0x9a000, 15, 0),
> > +	[110] = SDC_PINGROUP(sdc1_clk, 0x9a000, 13, 6),
> > +	[111] = SDC_PINGROUP(sdc1_cmd, 0x9a000, 11, 3),
> > +	[112] = SDC_PINGROUP(sdc1_data, 0x9a000, 9, 0),
> > +};
> > +
> > +static const struct msm_pinctrl_soc_data sdx55_pinctrl = {
> > +	.pins = sdx55_pins,
> > +	.npins = ARRAY_SIZE(sdx55_pins),
> > +	.functions = sdx55_functions,
> > +	.nfunctions = ARRAY_SIZE(sdx55_functions),
> > +	.groups = sdx55_groups,
> > +	.ngroups = ARRAY_SIZE(sdx55_groups),
> > +	.ngpios = 108,
> 
> If we had UFS_RESET, this should include it; i.e. be 109.

Okay will check and update

Thanks for quick review

-- 
~Vinod