Re: [PATCH v3 18/26] coresight: etm4x: Clean up exception level masks

Suzuki K Poulose
2020-11-09T09:44:15Z

On 11/6/20 6:52 PM, Mathieu Poirier wrote:
> Good morning,

Good morning.

>
> On Wed, Oct 28, 2020 at 10:09:37PM +0000, Suzuki K Poulose wrote:
>> etm4_get_access_type() calculates the exception level bits
>> for use in address comparator registers. This is also used
>> by the TRCVICTLR register by shifting to the required position.
>>
>> This patch cleans up the logic to make etm4_get_access_type()
>> calcualte a generic mask which can be used by all users by
>> shifting to their field.
>>
>> No functional changes, only code cleanups.
>>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> ---
>> Changes since previous version:
>> - Fix the duplicate shift. More commentary
>> ---

>> -/* access level control in TRCVICTLR - same bits as TRCACATRn but shifted */
>> -#define ETM_EXLEVEL_LSHIFT_TRCVICTLR 8
>> +/*
>> + * Exception level mask for Secure and Non-Secure ELs.
>> + * ETM defines the bits for EL control (e.g, TRVICTLR, TRCACTRn).
>> + * The Secure and Non-Secure ELs are always to gether.
>> + * Non-secure EL3 is never implemented.
>> + * We use the following generic mask as they appear in different
>> + * registers and this can be shifted for the appropriate
>> + * fields.
>> + */
>> +#define ETM_EXLEVEL_S_APP BIT(0) /* Secure EL0 */
>> +#define ETM_EXLEVEL_S_OS BIT(1) /* Secure EL1 */
>> +#define ETM_EXLEVEL_S_HYP BIT(2) /* Secure EL2 */
>> +#define ETM_EXLEVEL_S_MON BIT(3) /* Secure EL3/Montor */
>
> s/Montor/Monitor
>

>> +#define ETM_EXLEVEL_NS_APP BIT(4) /* NonSecure EL0 */
>> +#define ETM_EXLEVEL_NS_OS BIT(5) /* NonSecure EL1 */
>> +#define ETM_EXLEVEL_NS_HYP BIT(6) /* NonSecure EL2 */
>> +
>> +#define ETM_EXLEVEL_MASK (GENMASK(6, 0))
>
> Not used.
>
>> +#define ETM_EXLEVEL_S_MASK (GENMASK(3, 0))
>> +#define ETM_EXLEVEL_NS_MASK (GENMASK(6, 4))
>
> This needs to be GENMASK(2, 0) in order TRCVICTLR_EXLEVEL_NS_SHIFT to be 20.
> Otherwise the resulting mask is 4 bit off to the left.
>

Will address the comments. Thanks for spotting the mistakes.

Suzuki