From: Kishon Vijay Abraham I <kishon@ti.com>
To: Tero Kristo <t-kristo@ti.com>, Nishanth Menon <nm@ti.com>,
Rob Herring <robh+dt@kernel.org>, Roger Quadros <rogerq@ti.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>,
<linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH 2/2] arm64: dts: ti: k3-j721e-common-proc-board: Re-name "link" name as "phy"
Date: Wed, 4 Nov 2020 18:59:02 +0530 [thread overview]
Message-ID: <20201104132902.20377-3-kishon@ti.com> (raw)
In-Reply-To: <20201104132902.20377-1-kishon@ti.com>
Commit 66db854b1f62d ("arm64: dts: ti: k3-j721e-common-proc-board:
Configure the PCIe instances") and
commit 02c35dca2b488 ("arm64: dts: ti: k3-j721e: Enable Super-Speed
support for USB0") added PHY DT nodes with node name as "link"
However nodes with #phy-cells should be named 'phy'. Re-name
subnodes of serdes in J721E to 'phy'.
Link: http://lore.kernel.org/r/20200909203631.GA3026331@bogus
Link: http://lore.kernel.org/r/1603898561-5142-1-git-send-email-sjakhade@cadence.com
Fixes: 66db854b1f62d ("arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances")
Fixes: 02c35dca2b488 ("arm64: dts: ti: k3-j721e: Enable Super-Speed support for USB0")
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 52e121155563..e837614d8d88 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -325,7 +325,7 @@
};
&serdes3 {
- serdes3_usb_link: link@0 {
+ serdes3_usb_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
@@ -561,7 +561,7 @@
};
&serdes0 {
- serdes0_pcie_link: link@0 {
+ serdes0_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
@@ -571,7 +571,7 @@
};
&serdes1 {
- serdes1_pcie_link: link@0 {
+ serdes1_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
@@ -581,7 +581,7 @@
};
&serdes2 {
- serdes2_pcie_link: link@0 {
+ serdes2_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
--
2.17.1
prev parent reply other threads:[~2020-11-04 13:29 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-04 13:29 [PATCH 0/2] arm64: dts: ti: J721E: PCIe/SERDES DT Fixes Kishon Vijay Abraham I
2020-11-04 13:29 ` [PATCH 1/2] arm64: dts: ti: k3-j721e-main: Fix PCIe maximum outbound regions Kishon Vijay Abraham I
2020-11-04 13:29 ` Kishon Vijay Abraham I [this message]
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