From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 473E8C388F7 for ; Wed, 4 Nov 2020 14:10:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E2489221E2 for ; Wed, 4 Nov 2020 14:10:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1604499027; bh=fv6XfjHG8ZIIsa87jtEIKZWaWa19bUpBegHs0UJskMk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=KT708dzTelp+/4lMwfABitXG7hrSeD3myUG+EqG+TLN1yoACWBgOshZkfh49cp3vY 9JQy4M+wJsLOuTYee2epiZZKafhGlOOpwFhUpVvaa65v42neFfZ+46UEHQyDSPscrg Ab3spdGtQXXHRHKjWWiNzPxAu/JDKi8l59Av5DbA= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730037AbgKDOJ1 (ORCPT ); Wed, 4 Nov 2020 09:09:27 -0500 Received: from mail.kernel.org ([198.145.29.99]:37628 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729980AbgKDOJX (ORCPT ); Wed, 4 Nov 2020 09:09:23 -0500 Received: from ogabbay-VM.habana-labs.com (unknown [213.57.90.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 5467C2236F; Wed, 4 Nov 2020 14:09:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1604498962; bh=fv6XfjHG8ZIIsa87jtEIKZWaWa19bUpBegHs0UJskMk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FSG6+59ArlhD++hfW8cEM37Nd528pFuXXug9hcVFYzfjpledvPpqflnSLs4G2oSr6 ahM7dErxyvGr+wQyJJRixYcs77p1EHux/P0Qg4oHPMmvTQQf53hIhZ+CW2eG1BHkaD tTC5QbAM40XZu+KWIs2sybjtp36lC61svikXw+00= From: Oded Gabbay To: linux-kernel@vger.kernel.org Cc: SW_Drivers@habana.ai, Igor Grinberg Subject: [PATCH] habanalabs/gaudi: remove pcie_en strap toggle Date: Wed, 4 Nov 2020 16:09:00 +0200 Message-Id: <20201104140908.10178-4-ogabbay@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201104140908.10178-1-ogabbay@kernel.org> References: <20201104140908.10178-1-ogabbay@kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Igor Grinberg Since the very large grace period is over and this functionality prevents us to implement the new reset sequence and apply security settings, we need to remove the code toggling the PCIE_EN bit in the straps register. Remove it for good. Signed-off-by: Igor Grinberg Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- drivers/misc/habanalabs/gaudi/gaudi.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/drivers/misc/habanalabs/gaudi/gaudi.c b/drivers/misc/habanalabs/gaudi/gaudi.c index ae4f3669261d..c075f7f10843 100644 --- a/drivers/misc/habanalabs/gaudi/gaudi.c +++ b/drivers/misc/habanalabs/gaudi/gaudi.c @@ -3871,7 +3871,7 @@ static int gaudi_hw_init(struct hl_device *hdev) static void gaudi_hw_fini(struct hl_device *hdev, bool hard_reset) { struct gaudi_device *gaudi = hdev->asic_specific; - u32 status, reset_timeout_ms, cpu_timeout_ms, boot_strap = 0; + u32 status, reset_timeout_ms, cpu_timeout_ms; if (!hard_reset) { dev_err(hdev->dev, "GAUDI doesn't support soft-reset\n"); @@ -3903,16 +3903,6 @@ static void gaudi_hw_fini(struct hl_device *hdev, bool hard_reset) /* Tell ASIC not to re-initialize PCIe */ WREG32(mmPREBOOT_PCIE_EN, LKD_HARD_RESET_MAGIC); - boot_strap = RREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS); - - /* H/W bug WA: - * rdata[31:0] = strap_read_val; - * wdata[31:0] = rdata[30:21],1'b0,rdata[20:0] - */ - boot_strap = (((boot_strap & 0x7FE00000) << 1) | - (boot_strap & 0x001FFFFF)); - WREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS, boot_strap & ~0x2); - /* Restart BTL/BLR upon hard-reset */ if (hdev->asic_prop.fw_security_disabled) WREG32(mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START, 1); @@ -3935,8 +3925,6 @@ static void gaudi_hw_fini(struct hl_device *hdev, bool hard_reset) "Timeout while waiting for device to reset 0x%x\n", status); - WREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS, boot_strap); - if (gaudi) { gaudi->hw_cap_initialized &= ~(HW_CAP_CPU | HW_CAP_CPU_Q | HW_CAP_HBM | HW_CAP_PCI_DMA | -- 2.17.1