Re: [PATCH 27/36] tty: synclinkmp: Mark never checked 'readval' as __always_unused

Lee Jones
2020-11-05T08:43:49Z

On Thu, 05 Nov 2020, Jiri Slaby wrote:

> On 04. 11. 20, 20:35, Lee Jones wrote:
> > Fixes the following W=1 kernel build warning(s):
> >
> > drivers/tty/synclinkmp.c: In function ‘init_adapter’:
> > drivers/tty/synclinkmp.c:5167:6: warning: variable ‘readval’ set but not used [-Wunused-but-set-variable]
> >
> > Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> > Cc: Jiri Slaby <jirislaby@kernel.org>
> > Cc: paulkf@microgate.com
> > Signed-off-by: Lee Jones <lee.jones@linaro.org>
> > ---
> > drivers/tty/synclinkmp.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/tty/synclinkmp.c b/drivers/tty/synclinkmp.c
> > index 0ca738f61a35b..75f494bfdcbed 100644
> > --- a/drivers/tty/synclinkmp.c
> > +++ b/drivers/tty/synclinkmp.c
> > @@ -5165,7 +5165,7 @@ static bool init_adapter(SLMP_INFO *info)
> > /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
> > volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
> > - u32 readval;
> > + u32 __always_unused readval;
>
> Why not just remove readval completely as in other cases?

Because I don't know what the result would be.

Will the read still happen, or will the compiler optimise it away?

My changes should not affect any of the instructions i.e. the register
read must still take place

> And the loop can be turned into ndelay:
>
> /*
> * Force at least 170ns delay before clearing
> * reset bit. Each read from LCR takes at least
> * 30ns so 10 times for 300ns to be safe.
> */
> for(i=0;i<10;i++)
> readval = *MiscCtrl;

Again, since I can't test this, I do not want this patch to contain
any functional changes. AFAIC, the 10 register reads must still
happen after this patch is applied.

--
Lee Jones [李琼斯]
Senior Technical Lead - Developer Services
Linaro.org │ Open source software for Arm SoCs
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