Re: [PATCH v8 32/43] arm64: mte: Switch GCR_EL1 in kernel entry and exit

Catalin Marinas
2020-11-05T17:30:43Z

On Thu, Nov 05, 2020 at 12:18:47AM +0100, Andrey Konovalov wrote:
> diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c
> index 14b0c19a33e3..cc7e0f8707f7 100644
> --- a/arch/arm64/kernel/mte.c
> +++ b/arch/arm64/kernel/mte.c
> @@ -23,6 +23,8 @@
> #include <asm/ptrace.h>
> #include <asm/sysreg.h>
>
> +u64 gcr_kernel_excl __ro_after_init;
> +
> static void mte_sync_page_tags(struct page *page, pte_t *ptep, bool check_swap)
> {
> pte_t old_pte = READ_ONCE(*ptep);
> @@ -123,6 +125,23 @@ void *mte_set_mem_tag_range(void *addr, size_t size, u8 tag)
>
> void __init mte_init_tags(u64 max_tag)
> {
> + static bool gcr_kernel_excl_initialized = false;
> +
> + if (!gcr_kernel_excl_initialized) {
> + /*
> + * The format of the tags in KASAN is 0xFF and in MTE is 0xF.
> + * This conversion extracts an MTE tag from a KASAN tag.
> + */
> + u64 incl = GENMASK(FIELD_GET(MTE_TAG_MASK >> MTE_TAG_SHIFT,
> + max_tag), 0);
> +
> + gcr_kernel_excl = ~incl & SYS_GCR_EL1_EXCL_MASK;
> + gcr_kernel_excl_initialized = true;
> + }
> +
> + /* Enable the kernel exclude mask for random tags generation. */
> + write_sysreg_s(SYS_GCR_EL1_RRND | gcr_kernel_excl, SYS_GCR_EL1);

Same question as on a previous patch. Is SYS_GCR_EL1 written on the
other registers via cpu_enable_mte()?

--
Catalin