From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76C62C388F7 for ; Tue, 10 Nov 2020 14:49:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1FCAE206F1 for ; Tue, 10 Nov 2020 14:49:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="BUVwFjR1" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732274AbgKJOt0 (ORCPT ); Tue, 10 Nov 2020 09:49:26 -0500 Received: from esa3.microchip.iphmx.com ([68.232.153.233]:9035 "EHLO esa3.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731962AbgKJOtY (ORCPT ); Tue, 10 Nov 2020 09:49:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1605019764; x=1636555764; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ivjp1CbhHVITQi4NNYH/jJR1dyjRN3xPeVEdZV+zf8s=; b=BUVwFjR1BYXuoWqKcYUzUYBIrX8JgUY1wFJCtslQty6fYBU5hGqumGy4 yUXAem0cSXXKzhfz3d13FxU3QP7g3QNZygiqxVq4ROEQXziv4DaMIXI8P 8SDozmhSeqx7Ff3wyMyU+lQoJpRbter31XzIKw7uWsZqOiRymkWdQi8PN xLbkEMzVCNwO85TAVwDbXbfdQiDNdZlXub4sPK47IEk1eV3Vp4D5tTlrB CRhLVEywWz9NL/cGNi1z/ZWESEK2cuZd9yyFJ6QO+vvXnUg2Yc71SSPd2 0ps9Bvqaf/8NyqY86yyo5yRBQr8w7CU2BlZFkR0jVBCbPq5HrHl2ZfP3o Q==; IronPort-SDR: 2bvF2ltYIGQsaLHdWoDUzL0h/SKX05+x8v5p6Rokvz/mzvwdDzGIlz2jxLRza4pReNNLpkTRia OtwQ3WChxJkl7ifV38nIrnmdrDJydnaB1Fq9GjdCBL8GhirBehNIuUummn16gj5mQqlNvOdCZo HSHv9UvqbB6gwt5+WKY8xxSQOHYnw90p9Ly9rvztHXQgnLSBk9tpA/eq2z5t2PoALVK4iMIW9i 5gtYGhl9iVxABCSzqaNFdKvFhaUEfXqOja2QkV2XUxGRhpb/9gWavM+enSb8E6jWz79oGqmU6n QJs= X-IronPort-AV: E=Sophos;i="5.77,466,1596524400"; d="scan'208";a="98454903" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 10 Nov 2020 07:49:23 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Tue, 10 Nov 2020 07:49:23 -0700 Received: from mchp-dev-shegelun.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Tue, 10 Nov 2020 07:49:21 -0700 From: Steen Hegelund To: Kishon Vijay Abraham I , Vinod Koul CC: Steen Hegelund , Alexandre Belloni , Lars Povlsen , Bjarni Jonasson , Microsemi List , Microchip UNG Driver List , Subject: [PATCH v2 2/4] phy: Add ethernet serdes configuration option Date: Tue, 10 Nov 2020 15:49:08 +0100 Message-ID: <20201110144910.558164-3-steen.hegelund@microchip.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201110144910.558164-1-steen.hegelund@microchip.com> References: <20201110144910.558164-1-steen.hegelund@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Provide a new ethernet phy configuration structure, that allow PHYs used for ethernet to be configured with speed, media type and clock information. Signed-off-by: Lars Povlsen Signed-off-by: Steen Hegelund --- include/linux/phy/phy-ethernet-serdes.h | 49 +++++++++++++++++++++++++ include/linux/phy/phy.h | 4 ++ 2 files changed, 53 insertions(+) create mode 100644 include/linux/phy/phy-ethernet-serdes.h diff --git a/include/linux/phy/phy-ethernet-serdes.h b/include/linux/phy/phy-ethernet-serdes.h new file mode 100644 index 000000000000..04f496855b00 --- /dev/null +++ b/include/linux/phy/phy-ethernet-serdes.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Microchip Sparx5 Ethernet SerDes driver + * + * Copyright (c) 2020 Microschip Inc + */ +#ifndef __PHY_ETHERNET_SERDES_H_ +#define __PHY_ETHERNET_SERDES_H_ + +#include + +enum ethernet_media_type { + ETH_MEDIA_DEFAULT, + ETH_MEDIA_SR, + ETH_MEDIA_DAC, +}; + +/** + * struct phy_configure_opts_eth_serdes - Ethernet SerDes + * + * This structure is used to represent the configuration state of a + * Ethernet Serdes PHY. + */ +struct phy_configure_opts_eth_serdes { + /** + * @speed + * + * Speed of the serdes interface in Mbps + */ + u32 speed; + + /** + * @media_type + * + * Specifies which media the serdes will be using + */ + enum ethernet_media_type media_type; + + /** + * @clk + * + * Specifies the serdes clock in MHz + * Default: 0 will provide the highest supported clock. + */ + u32 clk; +}; + +#endif + diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index e435bdb0bab3..78ecb375cede 100644 --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h @@ -18,6 +18,7 @@ #include #include +#include struct phy; @@ -49,11 +50,14 @@ enum phy_mode { * * @mipi_dphy: Configuration set applicable for phys supporting * the MIPI_DPHY phy mode. + * @eth_serdes: Configuration set applicable for phys supporting + * the ethernet serdes. * @dp: Configuration set applicable for phys supporting * the DisplayPort protocol. */ union phy_configure_opts { struct phy_configure_opts_mipi_dphy mipi_dphy; + struct phy_configure_opts_eth_serdes eth_serdes; struct phy_configure_opts_dp dp; }; -- 2.29.2