[PATCH 1/7] dt-bindings: clock: add dt binding header for mt7621 clocks

Sergio Paracuellos
2020-11-11T16:30:49Z

Adds dt binding header for 'mediatek,mt7621-pll' PLL controller
and for 'mediatek,mt7621-clk' clock gates.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
include/dt-bindings/clock/mt7621-clk.h | 39 ++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
create mode 100644 include/dt-bindings/clock/mt7621-clk.h

diff --git a/include/dt-bindings/clock/mt7621-clk.h b/include/dt-bindings/clock/mt7621-clk.h
new file mode 100644
index 000000000000..8fccfa514185
--- /dev/null
+++ b/include/dt-bindings/clock/mt7621-clk.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT7621_H
+#define _DT_BINDINGS_CLK_MT7621_H
+
+/* SYS CLOCKS */
+#define MT7621_CLK_CPU 0
+#define MT7621_CLK_AHB 1
+#define MT7621_CLK_APB 2
+#define MT7621_CLK_MAX 3
+
+/* CLOCK GATES */
+#define MT7621_CLK_HSDMA 0
+#define MT7621_CLK_FE 1
+#define MT7621_CLK_SP_DIVTX 2
+#define MT7621_CLK_TIMER 3
+#define MT7621_CLK_INT 4
+#define MT7621_CLK_MC 5
+#define MT7621_CLK_PCM 6
+#define MT7621_CLK_PIO 7
+#define MT7621_CLK_GDMA 8
+#define MT7621_CLK_NAND 9
+#define MT7621_CLK_I2C 10
+#define MT7621_CLK_I2S 11
+#define MT7621_CLK_SPI 12
+#define MT7621_CLK_UART1 13
+#define MT7621_CLK_UART2 14
+#define MT7621_CLK_UART3 15
+#define MT7621_CLK_ETH 16
+#define MT7621_CLK_PCIE0 17
+#define MT7621_CLK_PCIE1 18
+#define MT7621_CLK_PCIE2 19
+#define MT7621_CLK_CRYPTO 20
+#define MT7621_CLK_SHXC 21
+
+#endif /* _DT_BINDINGS_CLK_MT7621_H */
--
2.25.1