From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4250C2D0E4 for ; Tue, 24 Nov 2020 19:16:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4DDCD208CA for ; Tue, 24 Nov 2020 19:16:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="HIY6XK7y" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404398AbgKXTQO (ORCPT ); Tue, 24 Nov 2020 14:16:14 -0500 Received: from m42-4.mailgun.net ([69.72.42.4]:42812 "EHLO m42-4.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2404264AbgKXTQL (ORCPT ); Tue, 24 Nov 2020 14:16:11 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1606245371; h=Content-Transfer-Encoding: MIME-Version: Message-Id: Date: Subject: Cc: To: From: Sender; bh=5buuSHSoW4H28tI/ERKmRVeWEk8S64oetvKCFJleVEE=; b=HIY6XK7y1VnrvjBAYh/H20FW1bqQYylVNU7rCd/xWZNmu1ebCNJJ3p3MA+9DLz2I78BGf3tJ omLpg6EdVmPXrFw7sj0OlfEMutRDW6wxxaRlqFY8rFWfQtuwjBC9sGDwgoY9eQ6BFdz6v905 PCu2amjmy+gnmtSvMoNozjZMIhQ= X-Mailgun-Sending-Ip: 69.72.42.4 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n07.prod.us-west-2.postgun.com with SMTP id 5fbd5bf91dba509aaeaf72e0 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Tue, 24 Nov 2020 19:16:09 GMT Sender: jcrouse=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id A8E6EC4331D; Tue, 24 Nov 2020 19:16:08 +0000 (UTC) Received: from jordan-laptop.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse) by smtp.codeaurora.org (Postfix) with ESMTPSA id 5FE67C433ED; Tue, 24 Nov 2020 19:16:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 5FE67C433ED Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: linux-arm-msm@vger.kernel.org Cc: Robin Murphy , iommu@lists.linux-foundation.org, Will Deacon , Akhil P Oommen , Bjorn Andersson , Daniel Vetter , David Airlie , Emil Velikov , Eric Anholt , Greg Kroah-Hartman , "Gustavo A. R. Silva" , Joerg Roedel , Jonathan Marek , Krishna Reddy , Rob Clark , Rob Clark , Sai Prakash Ranjan , Sean Paul , Sharat Masetty , Thomas Zimmermann , dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 0/3] iommu/arm-smmu: adreno-smmu page fault handling Date: Tue, 24 Nov 2020 12:15:57 -0700 Message-Id: <20201124191600.2051751-1-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This is a stack to add an Adreno GPU specific handler for pagefaults. The first patch starts by wiring up report_iommu_fault for arm-smmu. The next patch adds a adreno-smmu-priv function hook to capture a handful of important debugging registers such as TTBR0, CONTEXTIDR, FSYNR0 and others. This is used by the third patch to print more detailed information on page fault such as the TTBR0 for the pagetable that caused the fault and the source of the fault as determined by a combination of the FSYNR1 register and an internal GPU register. This code provides a solid base that we can expand on later for even more extensive GPU side page fault debugging capabilities. v2: Fix comment wording and function pointer check per Rob Clark Jordan Crouse (3): iommu/arm-smmu: Add support for driver IOMMU fault handlers drm/msm: Add an adreno-smmu-priv callback to get pagefault info drm/msm: Improve the a6xx page fault handler drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 76 +++++++++++++++++++++- drivers/gpu/drm/msm/msm_iommu.c | 11 +++- drivers/gpu/drm/msm/msm_mmu.h | 4 +- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 19 ++++++ drivers/iommu/arm/arm-smmu/arm-smmu.c | 16 ++++- drivers/iommu/arm/arm-smmu/arm-smmu.h | 2 + include/linux/adreno-smmu-priv.h | 31 ++++++++- 8 files changed, 151 insertions(+), 12 deletions(-) -- 2.25.1