From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24615C2D0E4 for ; Wed, 25 Nov 2020 01:21:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CFBC720665 for ; Wed, 25 Nov 2020 01:21:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728398AbgKYBVE (ORCPT ); Tue, 24 Nov 2020 20:21:04 -0500 Received: from vps0.lunn.ch ([185.16.172.187]:48628 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727692AbgKYBVD (ORCPT ); Tue, 24 Nov 2020 20:21:03 -0500 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1khjUG-008iCJ-SG; Wed, 25 Nov 2020 02:20:48 +0100 Date: Wed, 25 Nov 2020 02:20:48 +0100 From: Andrew Lunn To: Chris Packham Cc: vivien.didelot@gmail.com, f.fainelli@gmail.com, olteanv@gmail.com, davem@davemloft.net, kuba@kernel.org, linux@armlinux.org.uk, pavana.sharma@digi.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [net-next PATCH v5 3/4] net: dsa: mv88e6xxx: Add serdes interrupt support for MV88E6097 Message-ID: <20201125012048.GD2075216@lunn.ch> References: <20201124043440.28400-1-chris.packham@alliedtelesis.co.nz> <20201124043440.28400-4-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201124043440.28400-4-chris.packham@alliedtelesis.co.nz> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Nov 24, 2020 at 05:34:39PM +1300, Chris Packham wrote: > The MV88E6097 presents the serdes interrupts for ports 8 and 9 via the > Switch Global 2 registers. There is no additional layer of > enablinh/disabling the serdes interrupts like other mv88e6xxx switches. enabling > Even though most of the serdes behaviour is the same as the MV88E6185 > that chip does not provide interrupts for serdes events so unlike > earlier commits the functions added here are specific to the MV88E6097. > > Signed-off-by: Chris Packham Reviewed-by: Andrew Lunn Andrew