From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D441C63777 for ; Mon, 30 Nov 2020 17:14:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CAA072073C for ; Mon, 30 Nov 2020 17:14:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729326AbgK3RNy (ORCPT ); Mon, 30 Nov 2020 12:13:54 -0500 Received: from mail.kernel.org ([198.145.29.99]:38386 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725955AbgK3RNx (ORCPT ); Mon, 30 Nov 2020 12:13:53 -0500 Received: from gaia (unknown [95.146.230.165]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 133102073C; Mon, 30 Nov 2020 17:13:11 +0000 (UTC) Date: Mon, 30 Nov 2020 17:13:09 +0000 From: Catalin Marinas To: Vincenzo Frascino Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kasan-dev@googlegroups.com, Will Deacon Subject: Re: [PATCH v2] arm64: mte: Fix typo in macro definition Message-ID: <20201130171309.GG3902@gaia> References: <20201130170709.22309-1-vincenzo.frascino@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201130170709.22309-1-vincenzo.frascino@arm.com> User-Agent: Mutt/1.10.1 (2018-07-13) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Nov 30, 2020 at 05:07:09PM +0000, Vincenzo Frascino wrote: > UL in the definition of SYS_TFSR_EL1_TF1 was misspelled causing > compilation issues when trying to implement in kernel MTE async > mode. > > Fix the macro correcting the typo. > > Note: MTE async mode will be introduced with a future series. > > Fixes: c058b1c4a5ea ("arm64: mte: system register definitions") > Cc: Catalin Marinas > Cc: Will Deacon > Signed-off-by: Vincenzo Frascino > --- > arch/arm64/include/asm/sysreg.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index e2ef4c2edf06..801861d05426 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -987,7 +987,7 @@ > #define SYS_TFSR_EL1_TF0_SHIFT 0 > #define SYS_TFSR_EL1_TF1_SHIFT 1 > #define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT) > -#define SYS_TFSR_EL1_TF1 (UK(2) << SYS_TFSR_EL1_TF1_SHIFT) > +#define SYS_TFSR_EL1_TF1 (UL(1) << SYS_TFSR_EL1_TF1_SHIFT) I think we should first rename it to EU and then fix it properly ;). While nothing breaks without this patch currently, we should merge it as a fix. Acked-by: Catalin Marinas Thanks.