From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EA77C64E7A for ; Tue, 1 Dec 2020 09:40:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E78F72064C for ; Tue, 1 Dec 2020 09:40:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387635AbgLAJku (ORCPT ); Tue, 1 Dec 2020 04:40:50 -0500 Received: from mga14.intel.com ([192.55.52.115]:47939 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387547AbgLAJkt (ORCPT ); Tue, 1 Dec 2020 04:40:49 -0500 IronPort-SDR: 1eozpUpPMfxYv4vI+Vd+E4qeyIJj/uY2BNLbpTYv0rFiJVJVXSuqzM1bzxtP22ISmMzY4jje0R kAjb1ZZEPTsA== X-IronPort-AV: E=McAfee;i="6000,8403,9821"; a="172012362" X-IronPort-AV: E=Sophos;i="5.78,384,1599548400"; d="scan'208";a="172012362" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Dec 2020 01:40:08 -0800 IronPort-SDR: PlkjibYV/xFBCM+5rPf/j3UtTlYiT8WDfSMywmrUCAU8maOR84Fw0UIX5RNInG4/r8B01YWw83 ytUhoFr5Qpow== X-IronPort-AV: E=Sophos;i="5.78,384,1599548400"; d="scan'208";a="335030162" Received: from shsi6026.sh.intel.com (HELO localhost) ([10.239.147.88]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Dec 2020 01:40:03 -0800 From: shuo.a.liu@intel.com To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Greg Kroah-Hartman , "H . Peter Anvin" , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Sean Christopherson , Yu Wang , Reinette Chatre , Shuo Liu , Yakui Zhao , Nick Desaulniers , Dave Hansen , Dan Williams , Fengwei Yin , Zhi Wang , Zhenyu Wang , Arvind Sankar , Peter Zijlstra , Segher Boessenkool Subject: [PATCH v6 04/18] x86/acrn: Introduce hypercall interfaces Date: Tue, 1 Dec 2020 17:38:39 +0800 Message-Id: <20201201093853.12070-5-shuo.a.liu@intel.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201201093853.12070-1-shuo.a.liu@intel.com> References: <20201201093853.12070-1-shuo.a.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Shuo Liu The Service VM communicates with the hypervisor via conventional hypercalls. VMCALL instruction is used to make the hypercalls. ACRN hypercall ABI: * Hypercall number is in R8 register. * Up to 2 parameters are in RDI and RSI registers. * Return value is in RAX register. Introduce the ACRN hypercall interfaces. Because GCC doesn't support R8 register as direct register constraints, use supported constraint as input with a explicit MOV to R8 in beginning of asm. Originally-by: Yakui Zhao Signed-off-by: Shuo Liu Reviewed-by: Reinette Chatre Reviewed-by: Nick Desaulniers Cc: Dave Hansen Cc: Sean Christopherson Cc: Dan Williams Cc: Fengwei Yin Cc: Zhi Wang Cc: Zhenyu Wang Cc: Yu Wang Cc: Reinette Chatre Cc: Greg Kroah-Hartman Cc: Borislav Petkov Cc: Arvind Sankar Cc: Peter Zijlstra Cc: Nick Desaulniers Cc: Segher Boessenkool --- arch/x86/include/asm/acrn.h | 54 +++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/x86/include/asm/acrn.h b/arch/x86/include/asm/acrn.h index 127f20672c5d..e003a01b7c67 100644 --- a/arch/x86/include/asm/acrn.h +++ b/arch/x86/include/asm/acrn.h @@ -21,4 +21,58 @@ static inline u32 acrn_cpuid_base(void) return 0; } +/* + * Hypercalls for ACRN + * + * - VMCALL instruction is used to implement ACRN hypercalls. + * - ACRN hypercall ABI: + * - Hypercall number is passed in R8 register. + * - Up to 2 arguments are passed in RDI, RSI. + * - Return value will be placed in RAX. + * + * Because GCC doesn't support R8 register as direct register constraints, use + * supported constraint as input with a explicit MOV to R8 in beginning of asm. + */ +static inline long acrn_hypercall0(unsigned long hcall_id) +{ + long result; + + asm volatile("movl %1, %%r8d\n\t" + "vmcall\n\t" + : "=a" (result) + : "g" (hcall_id) + : "r8", "memory"); + + return result; +} + +static inline long acrn_hypercall1(unsigned long hcall_id, + unsigned long param1) +{ + long result; + + asm volatile("movl %1, %%r8d\n\t" + "vmcall\n\t" + : "=a" (result) + : "g" (hcall_id), "D" (param1) + : "r8", "memory"); + + return result; +} + +static inline long acrn_hypercall2(unsigned long hcall_id, + unsigned long param1, + unsigned long param2) +{ + long result; + + asm volatile("movl %1, %%r8d\n\t" + "vmcall\n\t" + : "=a" (result) + : "g" (hcall_id), "D" (param1), "S" (param2) + : "r8", "memory"); + + return result; +} + #endif /* _ASM_X86_ACRN_H */ -- 2.28.0