Re: [PATCH v2 01/10] dt-bindings: mstar: Add binding details for mstar,smpctrl

Rob Herring
2020-12-09T16:36:38Z

On Tue, Dec 01, 2020 at 10:43:21PM +0900, Daniel Palmer wrote:
> This adds a YAML description of the smpctrl node needed by the
> platform code for the MStar/SigmaStar Armv7 SoCs to boot secondary cpus.

You need an 'enable-method' string defined too.

>
> Signed-off-by: Daniel Palmer <daniel@0x0f.com>
> ---
> .../bindings/arm/mstar/mstar,smpctrl.yaml | 40 +++++++++++++++++++
> 1 file changed, 40 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml b/Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml
> new file mode 100644
> index 000000000000..599c65980f5d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml
> @@ -0,0 +1,40 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright 2020 thingy.jp.
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/arm/mstar/mstar,smpctrl.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: MStar/SigmaStar Armv7 SoC SMP control registers
> +
> +maintainers:
> + - Daniel Palmer <daniel@thingy.jp>
> +
> +description: |
> + MStar/SigmaStar's Armv7 SoCs that have more than one processor
> + have a region of registers that allow setting the boot address
> + and a magic number that allows secondary processors to leave
> + the loop they are parked in by the boot ROM.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - sstar,ssd201-smpctrl # SSD201/SSD202D
> + - const: mstar,smpctrl
> +
> + reg:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + smpctrl@204000 {
> + compatible = "sstar,ssd201-smpctrl", "mstar,smpctrl";
> + reg = <0x204000 0x200>;
> + };
> --
> 2.29.2
>