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Tue, 15 Dec 2020 07:34:48 +0000 From: Suravee Suthikulpanit To: linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org Cc: joro@8bytes.org, will@kernel.org, Suravee Suthikulpanit Subject: [PATCH v4 08/13] iommu/amd: Remove amd_iommu_domain_get_pgtable Date: Tue, 15 Dec 2020 01:37:00 -0600 Message-Id: <20201215073705.123786-9-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201215073705.123786-1-suravee.suthikulpanit@amd.com> References: <20201215073705.123786-1-suravee.suthikulpanit@amd.com> Content-Type: text/plain X-Originating-IP: [165.204.78.2] X-ClientProxiedBy: SN2PR01CA0060.prod.exchangelabs.com (2603:10b6:800::28) To BYAPR12MB4597.namprd12.prod.outlook.com (2603:10b6:a03:10b::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from ethanolx5673host.amd.com (165.204.78.2) by SN2PR01CA0060.prod.exchangelabs.com (2603:10b6:800::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3654.12 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: =?us-ascii?Q?b6KyffLcoV/dAzvu0A7SvLZDvET4IAJpS96KPS1UW7Oi3PR2UZZQsDqisdck?= =?us-ascii?Q?Vk12Kt/VTT/Q03iUCGpVzgzAUvcB4jn19lRhOMva7ogYnpoHHAGVWqwlvSP4?= =?us-ascii?Q?0H0Ocpd/q1EWvPt6Et7LGqwi8WfNRRfrHZD6na10I3aLpydqNZMlZtl38uZG?= =?us-ascii?Q?bWLEOLVEOX4CGVXW6WyoEUV3MLK4hYygRnW8kMPTjbKTSIo4UEdkNx35z9AG?= =?us-ascii?Q?kErai4sbRRRh9DDs9gX4VqnPb7RyDq8JxEK7l+bf6cIW/KwGZixHwYe+i8mu?= =?us-ascii?Q?ooBXnWZn7PAXxViGnthFc6ODa4UdPj6b9bZa7XFKLdANnfBlOdLseCUURpUV?= =?us-ascii?Q?NMONBfdknxaHWNBsVuUqJgdPloLRc4Y29z9//GHbZPYsb4nSYO0Q6eFkwgLX?= =?us-ascii?Q?NtLc1ED31Zh7tUtPLs0KGpdsIZaUpt3dGM2p/9gc+j1ZdfwJy+pVhJVAXbor?= =?us-ascii?Q?Vvl+xa3az/baM50NgojQQWIiqDJhBLAnZw0BJvHPgaekws+ASryuuDHiIrjl?= =?us-ascii?Q?jjcopKuDHx2OvdalDvCIM9aGn/fjv+PmHe/N8J5LZxeDPN4o3Lx60EvyAozH?= =?us-ascii?Q?y08yeb7sfuFht+du6T++WQS/8m/noc4ITHbzF6xI8s6ebXURP6v5yl2yR7XV?= =?us-ascii?Q?jNxaBP8ISQtxQXqgvfqlEi+/5N9tzmTz0MSdgjKnxuKnjW7njf5yJ6GD/Uv3?= =?us-ascii?Q?OGjTs/j0nVtIDJJbakWVbZbInLWm8brEkXleUVVAoITZx2oMqHE+WRTXJPrV?= =?us-ascii?Q?Gnyhu2sTzP/OlHBvTWkosJhd2NUHqqeU71APU0OlsBMuvQgSh1kryNVqhsZT?= =?us-ascii?Q?MBK0Yjuw308ggbEEiZLzkRJKv/PLnP8uyZoNqbcyfDT6TF7Uvltfehc3Fbak?= =?us-ascii?Q?4fA20N3lz89NJB8nJB2q8gJcismD/Seb4C/s6E7+EI1yu4AjN2sHWx/dRDlj?= =?us-ascii?Q?q6xpBoQpDXLz5fGcCqCgqqS2tiHMjvqeAiXIRsZ/90s=3D?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthSource: BYAPR12MB4597.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Dec 2020 07:34:47.6621 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-Network-Message-Id: ecff399b-8064-4474-b754-08d8a0cbe69a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 2GZfacovfiRDodl0xnzLo/9mJrdqbiQuaHSVuhxDYADiCGHHRsO6XmiWYm4JiGJR+l6BKhgH5NAq29RDm09ZCg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3127 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Since the IO page table root and mode parameters have been moved into the struct amd_io_pg, the function is no longer needed. Therefore, remove it along with the struct domain_pgtable. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 4 ++-- drivers/iommu/amd/amd_iommu_types.h | 6 ----- drivers/iommu/amd/io_pgtable.c | 36 ++++++++++------------------- drivers/iommu/amd/iommu.c | 34 ++++----------------------- 4 files changed, 19 insertions(+), 61 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 91d098003f12..76276d9e463c 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -110,6 +110,8 @@ static inline void amd_iommu_domain_set_pt_root(struct protection_domain *domain, u64 root) { atomic64_set(&domain->iop.pt_root, root); + domain->iop.root = (u64 *)(root & PAGE_MASK); + domain->iop.mode = root & 7; /* lowest 3 bits encode pgtable mode */ } static inline @@ -144,8 +146,6 @@ extern unsigned long iommu_unmap_page(struct protection_domain *dom, extern u64 *fetch_pte(struct protection_domain *domain, unsigned long address, unsigned long *page_size); -extern void amd_iommu_domain_get_pgtable(struct protection_domain *domain, - struct domain_pgtable *pgtable); extern void amd_iommu_domain_set_pgtable(struct protection_domain *domain, u64 *root, int mode); #endif diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h index 7c971c76d685..6897567d307e 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -518,12 +518,6 @@ struct protection_domain { unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */ }; -/* For decocded pt_root */ -struct domain_pgtable { - int mode; - u64 *root; -}; - /* * Structure where we save information about one hardware AMD IOMMU in the * system. diff --git a/drivers/iommu/amd/io_pgtable.c b/drivers/iommu/amd/io_pgtable.c index dc674e79ddf0..d4d131e43dcd 100644 --- a/drivers/iommu/amd/io_pgtable.c +++ b/drivers/iommu/amd/io_pgtable.c @@ -184,30 +184,27 @@ static bool increase_address_space(struct protection_domain *domain, unsigned long address, gfp_t gfp) { - struct domain_pgtable pgtable; unsigned long flags; bool ret = true; u64 *pte; spin_lock_irqsave(&domain->lock, flags); - amd_iommu_domain_get_pgtable(domain, &pgtable); - - if (address <= PM_LEVEL_SIZE(pgtable.mode)) + if (address <= PM_LEVEL_SIZE(domain->iop.mode)) goto out; ret = false; - if (WARN_ON_ONCE(pgtable.mode == PAGE_MODE_6_LEVEL)) + if (WARN_ON_ONCE(domain->iop.mode == PAGE_MODE_6_LEVEL)) goto out; pte = (void *)get_zeroed_page(gfp); if (!pte) goto out; - *pte = PM_LEVEL_PDE(pgtable.mode, iommu_virt_to_phys(pgtable.root)); + *pte = PM_LEVEL_PDE(domain->iop.mode, iommu_virt_to_phys(domain->iop.root)); - pgtable.root = pte; - pgtable.mode += 1; + domain->iop.root = pte; + domain->iop.mode += 1; amd_iommu_update_and_flush_device_table(domain); amd_iommu_domain_flush_complete(domain); @@ -215,7 +212,7 @@ static bool increase_address_space(struct protection_domain *domain, * Device Table needs to be updated and flushed before the new root can * be published. */ - amd_iommu_domain_set_pgtable(domain, pte, pgtable.mode); + amd_iommu_domain_set_pgtable(domain, pte, domain->iop.mode); ret = true; @@ -232,29 +229,23 @@ static u64 *alloc_pte(struct protection_domain *domain, gfp_t gfp, bool *updated) { - struct domain_pgtable pgtable; int level, end_lvl; u64 *pte, *page; BUG_ON(!is_power_of_2(page_size)); - amd_iommu_domain_get_pgtable(domain, &pgtable); - - while (address > PM_LEVEL_SIZE(pgtable.mode)) { + while (address > PM_LEVEL_SIZE(domain->iop.mode)) { /* * Return an error if there is no memory to update the * page-table. */ if (!increase_address_space(domain, address, gfp)) return NULL; - - /* Read new values to check if update was successful */ - amd_iommu_domain_get_pgtable(domain, &pgtable); } - level = pgtable.mode - 1; - pte = &pgtable.root[PM_LEVEL_INDEX(level, address)]; + level = domain->iop.mode - 1; + pte = &domain->iop.root[PM_LEVEL_INDEX(level, address)]; address = PAGE_SIZE_ALIGN(address, page_size); end_lvl = PAGE_SIZE_LEVEL(page_size); @@ -330,19 +321,16 @@ u64 *fetch_pte(struct protection_domain *domain, unsigned long address, unsigned long *page_size) { - struct domain_pgtable pgtable; int level; u64 *pte; *page_size = 0; - amd_iommu_domain_get_pgtable(domain, &pgtable); - - if (address > PM_LEVEL_SIZE(pgtable.mode)) + if (address > PM_LEVEL_SIZE(domain->iop.mode)) return NULL; - level = pgtable.mode - 1; - pte = &pgtable.root[PM_LEVEL_INDEX(level, address)]; + level = domain->iop.mode - 1; + pte = &domain->iop.root[PM_LEVEL_INDEX(level, address)]; *page_size = PTE_LEVEL_PAGE_SIZE(level); while (level > 0) { diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 37ecedce2c14..2963a37b7c16 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -139,15 +139,6 @@ static struct protection_domain *to_pdomain(struct iommu_domain *dom) return container_of(dom, struct protection_domain, domain); } -void amd_iommu_domain_get_pgtable(struct protection_domain *domain, - struct domain_pgtable *pgtable) -{ - u64 pt_root = atomic64_read(&domain->iop.pt_root); - - pgtable->root = (u64 *)(pt_root & PAGE_MASK); - pgtable->mode = pt_root & 7; /* lowest 3 bits encode pgtable mode */ -} - static struct iommu_dev_data *alloc_dev_data(u16 devid) { struct iommu_dev_data *dev_data; @@ -1484,7 +1475,6 @@ static void clear_dte_entry(u16 devid) static void do_attach(struct iommu_dev_data *dev_data, struct protection_domain *domain) { - struct domain_pgtable pgtable; struct amd_iommu *iommu; bool ats; @@ -1500,7 +1490,6 @@ static void do_attach(struct iommu_dev_data *dev_data, domain->dev_cnt += 1; /* Update device table */ - amd_iommu_domain_get_pgtable(domain, &pgtable); set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2); clone_aliases(dev_data->pdev); @@ -1827,10 +1816,7 @@ void amd_iommu_update_and_flush_device_table(struct protection_domain *domain) void amd_iommu_domain_update(struct protection_domain *domain) { - struct domain_pgtable pgtable; - /* Update device table */ - amd_iommu_domain_get_pgtable(domain, &pgtable); amd_iommu_update_and_flush_device_table(domain); /* Flush domain TLB(s) and wait for completion */ @@ -2080,12 +2066,10 @@ static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, gfp_t gfp) { struct protection_domain *domain = to_pdomain(dom); - struct domain_pgtable pgtable; int prot = 0; int ret; - amd_iommu_domain_get_pgtable(domain, &pgtable); - if (pgtable.mode == PAGE_MODE_NONE) + if (domain->iop.mode == PAGE_MODE_NONE) return -EINVAL; if (iommu_prot & IOMMU_READ) @@ -2105,10 +2089,8 @@ static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, struct iommu_iotlb_gather *gather) { struct protection_domain *domain = to_pdomain(dom); - struct domain_pgtable pgtable; - amd_iommu_domain_get_pgtable(domain, &pgtable); - if (pgtable.mode == PAGE_MODE_NONE) + if (domain->iop.mode == PAGE_MODE_NONE) return 0; return iommu_unmap_page(domain, iova, page_size); @@ -2119,11 +2101,9 @@ static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, { struct protection_domain *domain = to_pdomain(dom); unsigned long offset_mask, pte_pgsize; - struct domain_pgtable pgtable; u64 *pte, __pte; - amd_iommu_domain_get_pgtable(domain, &pgtable); - if (pgtable.mode == PAGE_MODE_NONE) + if (domain->iop.mode == PAGE_MODE_NONE) return iova; pte = fetch_pte(domain, iova, &pte_pgsize); @@ -2493,11 +2473,9 @@ static u64 *__get_gcr3_pte(u64 *root, int level, u32 pasid, bool alloc) static int __set_gcr3(struct protection_domain *domain, u32 pasid, unsigned long cr3) { - struct domain_pgtable pgtable; u64 *pte; - amd_iommu_domain_get_pgtable(domain, &pgtable); - if (pgtable.mode != PAGE_MODE_NONE) + if (domain->iop.mode != PAGE_MODE_NONE) return -EINVAL; pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); @@ -2511,11 +2489,9 @@ static int __set_gcr3(struct protection_domain *domain, u32 pasid, static int __clear_gcr3(struct protection_domain *domain, u32 pasid) { - struct domain_pgtable pgtable; u64 *pte; - amd_iommu_domain_get_pgtable(domain, &pgtable); - if (pgtable.mode != PAGE_MODE_NONE) + if (domain->iop.mode != PAGE_MODE_NONE) return -EINVAL; pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); -- 2.17.1